Cadence Intros Verification Solution with Integrated Formal Analysis and Simulation Capabilities

Cadence Design Systems, which provides electronic design solutions, announced Cadence Incisive Enterprise Verifier, an integrated verification solution delivering dual power of formal analysis and simulation engines.

 

According to company officials, “the IEV helps design and verification engineers find deep corner-case bugs and hit elusive coverage points missed by stand-alone formal or simulation.”

 

IEV enables the detection of more bugs and the exercise of more coverage metrics early in the project, before a test-bench is available. This process increases productivity through faster bring-up of designs and faster bug detection, company officials said.

 

Further, Cadence IEV boosts predictability by generating more metrics to assist with verification closure, and improves quality by finding more bugs in the design, according to company executives.

 

IEV integrates simulation and formal capabilities, which allows engineers to leverage assertions in new ways. The assertion used in formal analysis can be automatically used by the simulation engine to generate new stimulus for the design.

 

The solution also allows automatic switching between the formal and simulation engines to leverage both the rapid design exploration of simulation and the verification thoroughness of formal analysis. As a result, design and verification engineers get a higher return from assertions.

 

IEV provides automatic operation for most users, fine-grained control for expert users, and assertion debug capabilities. The solution also supports verification planning, regression operation on server farms, multi-core performance improvements, and consolidation of metrics gathered from regression runs. The solution links to Incisive Enterprise Manager for metric-driven verification across large projects.

 

“The challenge of performing thorough, efficient verification on today's designs is growing right along with the size and complexity of the designs themselves,” said Tom Anderson, product marketing director for enterprise verification at Cadence, in a statement.

 

The Incisive Enterprise Verifier should be of interest to any company seeking to boost its verification program, Anderson added. “This new product expands the scope of assertion-based verification, finding more bugs and driving more quickly toward verification closure.”

 

In July, TMCnet reported that Freescale Semiconductor has successfully taped out a 45-nanometer networking design using the Cadence ‘correct-by-design’ prevention, analysis, implementation and signoff solution.