Freescale Achieves Design Cycle Reduction with Cadence Design Solutions

Cadence Design Systems, a provider of electronic design solutions, announced that Freescale Semiconductor has successfully taped out a 45-nanometer networking design using the Cadence ‘correct-by-design’ prevention, analysis, implementation and signoff solution.

 

This design methodology demonstrated faster turnaround time compared to traditional design for manufacturing solutions, officials said. The methodology was used to tape out the design to Chartered Semiconductor Manufacturing to support that company’s vision is to accurately model manufacturing efforts and address them during the design phase.

 

The design flow incorporates Cadence’ model-based design-for-manufacturing prevention, analysis and signoff, including Cadence Litho Physical Analyzer, Cadence CMP Predictor, Cadence Litho Electrical Analyzer, Cadence QRC Extraction, and model-based routing optimization with the Cadence Encounter Digital Implementation System.

 

Cadence solutions leverage multi-core distributed processing to seamlessly address increasing design cycle and database size increases at 45- and 32-nanometer process nodes and have proven to deliver near-linear scalability.

 

The Litho Electrical Analyzer, according to officials, is the industry’s first electrical DFM solution in production use at leading semiconductor companies from 90 nanometers down to 40 nanometers. It currently facilitates 32- and 28-nanometer variability-aware library development.

 

Kyle Patterson, manager of DFM Technologies at Freescale Semiconductor (News - Alert), said, “For high-volume designs using advanced process nodes, we believe it is a key enabler and differentiator to have silicon-accurate analysis and implementation of yield-critical steps such as lithography and CMP.”

 

By incorporating Cadence advanced DFM techniques and with a methodology that takes a fraction of the time compared to traditional DFM methods, Freescale is able to accurately predict manufacturing issues and prevent them from occurring, Patterson added. Ultimately, this allows Freescale to accelerate the time-to-market and time-to-volume requirements, Patterson said.

 

Cadence officials believe that through collaborations with leading semiconductor companies such as Freescale, Cadence has developed one of the industry’s most complete DFM prevention, analysis and signoff methodologies, enabling design-side optimizations that reduce manufacturing risk.

 

“The design complexity and stringent manufacturing budgets at 45- and 32-nanometers require early three-way collaboration between the customer, the foundry and EDA, beginning at the library level,” said Dave Desharnais, group director of Digital Implementation Solutions at Cadence, in a statement.

 

“We are pleased that our silicon-proven technology has enabled Freescale’s design success and look forward to ensuring their continued design closure successes,” Desharnais said. “Cadence will continue to invest to be a leading provider of the entire manufacturability-aware implementation flow.”

 

In another major development, STMicroelectronics, which develops System-on-Chip and semiconductor solutions, has adopted the complete Cadence integrated signoff solutions consisting of QRC Extraction and Encounter Timing System, for 65- and 45-nanometer design, and is actively qualifying the system for 32-nanometer process technologies.

 

Commenting on this development, Chi-Ping Hsu, senior vice president of Implementation Products at Cadence, said, “Our vision to integrate production-proven signoff technologies directly with our design implementation solution is an industry first and a great technology advancement to address design closure challenges with advanced process nodes.”