Cadence Intros Latest Version of Allegro Technology

Cadence Design Systems (News - Alert), Inc. has recently unveiled the latest version of its Allegro PCB and IC packaging technology with exclusive features and capabilities that would significantly increase both productivity and predictability across silicon, SoC and system development.

The company has introduced the latest Allegro 16.5 features and capabilities to bring together the co-design and analysis between engineers involved in Silicon, SoC, and System Realization, and enabling more predictable and efficient design flows that deliver higher-quality end products.

The latest technologies include advanced miniaturization capabilities, uniquely integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design features, and flexible team-design enablement that would boost designer’s capability to heights.

“Coming on the first anniversary of the announcement of the EDA360 vision, our Allegro 16.5 release strengthens the connection between Silicon, SoC and System Realization -- the three key tenets of EDA360,” said John Bruggeman, senior vice president and CMO of Cadence.

He said that they have leveraged their leadership in PCB and IC package design to drive a true end-to-end flow across all product creation disciplines, which speeds time to market while improving productivity and profitability for the customers.

“We partnered with Cadence for the past 18 months to ensure that maximum functionality is available to our joint customers in the latest version of Allegro to support our ECP technology,” said Mark Beesley, director of Advanced Packaging ECP, AT & S. “ECP is used to enable further miniaturization of electronic devices while at the same time improving electrical performance of critical signals in a cost-effective manner.”

The company also announced that the Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, thus optimizing total cost-of-ownership.

In other news, Cadence Design Systems, Inc. unveiled significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities is said to expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.