Cadence Unveils Capabilities to Boost Verification Productivity

Cadence Design Systems, Inc., an electronic design automation (EDA) software and engineering services company, unveiled significant new advancements to help boost verification productivity for ASIC and FPGA designers.

Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities is said to expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

"Engine-level performance alone is simply not enough to solve the verification problem," Thomas Anderson, product management group director at Cadence said in a statement.

"Verification has fractured into niches during the past decade as complexity increased and teams needed to focus. This prevented a unified verification flow, making it very difficult to predict the verification process or know where in that process any particular project was. Our metric-driven approach, with the help of these new enhancements, changes all that with a unified verification plan, flow and metrics," Anderson added.

Cadence announcement on new capabilities is said to target inefficiencies that exist in verification flows for many of today's advanced node designs. The company is of the opinion that with the growth of design complexity, verification flows have often become fractured and inefficient, with separate niche flows created to address such challenges as mixed-signal, low-power and formal analysis. The new capabilities is believed to bind these niches through MDV and novel technology that supports the unique end-to-end Cadence approach to Silicon Realization which is a key tenet of the EDA360 vision that focuses on unified intent, abstraction and convergence.

Cadence also said that with the new release of the Incisive technology, verification engineers can merge coverage data from formal analysis and simulation engines within a unified verification plan. Additional abilities that expand the scope of the verification intent include support for enhanced low-power corruption and isolation simulation as well as automation for combining and mixing simulation and formal technologies.

With this latest technology, earlier bug detection is enabled through additional abstraction capability, including support of the forthcoming UVM 1.0 standard for testbench verification. Leveraging 10 years of experience with methodology leading to the UVM, Cadence said in a statement that it is offering now additional methodology support and metrics collection based on the UVM, including low-power, mixed-signal, and acceleration methodologies. Features such as validation of digital mixed-signal models against detailed transistor models, debug support for macros and finite state machines, and reference implementations of these methodologies in the Incisive Verification Kit enable project teams to improve their productivity.

For customers running thousands of regression tests, the new Incisive Specman Advanced Option is said to offer reseeding and dynamic loading of e-based tests, multi-core e code compilation, and the ability to shorten debug mixing interpreted and compiled code improving overall productivity by greater than 1.4 times. Other capabilities to speed convergence include support for multi-core formal analysis and 1.3-times faster SystemVerilog testbench simulations.