Open-Silicon Uses Cadence Silicon Realization Technology

Cadence Silicon Realization product line has been utilized by Open-Silicon, Inc. to successfully tape out a breakthrough high-performance processor at over 2.4GHz under typical conditions. Cadence's integrated end-to-end Encounter digital design, implementation, and manufacturability signoff technology was used by Open-Silicon to complete the entire design. An announcement in this regard has been made by the subsidiary of Cadence Design Systems (News - Alert), Inc., Cadence Design Systems India Pvt Ltd. Open-Silicon is a top semiconductor company focused on design, develop-to-spec, and derivative ICs.

In a release, Taher Madraswala, vice president of engineering at Open-Silicon said, "Cadence offers a complete suite of tools for designing ASICs and strong customer support. We have fine tuned the tools and found good results from synthesis through to tapeout. Cadence's Silicon Realization technology has also been a key contributor to our ongoing efforts to increase our predictability and reliability, both of which are critical to the Open-Silicon custom silicon solution."

Products where performance, power and time-to-market are important use Open-Silicon’s chips. Logical, physical, electrical, and manufacturing effects are concurrently optimized by Cadence's Silicon Realization product line. Iteration is therefore eliminated without sacrificing design quality. Timing sensitivity, yield variation, and leakage power from the start are addressed for the same. The objectives of performance, power, and cost are therefore achieved.

In a release, Dr. Naveed Sherwani who is the president and CEO of Open-Silicon, Inc. said, "We see Cadence as a key collaborator for Open-Silicon as we move towards 28-nanometer design and as the industry moves towards a design-lite model. We are confident that working with Cadence will help us achieve our customers' specific goals."

A new holistic approach to Silicon Realization has been recently announced by Cadence. A streamlined end-to-end path of integrated technology, tools, and methodology has been introduced for chip development. This is a shift from the traditional patchwork of point tools.

Products and technologies that deliver on the three essential requirements for a deterministic path to silicon will be offered by the new approach. The three essential requirements are unified design intent, abstraction and convergence. Cadence EDA360 strategy has the new approach as its key element. While reducing risk, this approach is also aimed at boosting productivity, predictability and profitability.