Mindspeed Details Next Generation Baseband of System-on-Chip Processor for 4G Base Stations

This week at the Hot Chip 22 conference (www.hotchips.org) at Stanford University in Palo Alto (News - Alert), Calif., Mindspeed Technologies, Inc.(www.mindspeed.com) presented a new family of system-on-chip (SoC) baseband processor, labeled Transcede, for next generation 3G/4G wireless base stations.

 
Designed to address the computational challenges of explosive video traffic across mobile networks around the world, the Transcede SoC processor integrates 26 programmable processor cores into a single chip, including two ARM (News - Alert) Cortex-A9 multi-core symmetric multiprocessing RISC cores, 10 CEVA DSP cores and ten DSP accelerators that support the complete wideband code-division multiple access (W-CDMA), TD-SCDMA, LTE or WiMAX (News - Alert) (Layers 1, 2 and above) processing needs of single- and multi-sector base stations.

Implemented in 40 nm TSMC process, the Transcede 4000 features 750 MHz processor cores and consumes only 12 W average power. Internally, it employs an AXI network to link its cores and peripherals and integrates L1 and L2 caches. For external links, the Transcede 4000 uses 10 high-speed cerdes, PCI (News - Alert) Express and serial Rapid I/Os.

In a company release, Chief Technology Officer James Johnston said, "The increasing use of smart phones and the surge of mobile video applications are key contributors to the network capacity crunch that many 3G subscribers are experiencing." He added that, "3G and 4G network operators are looking to migrate to a more flexible cellular landscape, which can accommodate compact base stations, such as microcells, picocells and metro femtocells. Mindspeed has designed the Transcede family of baseband processors to enable tomorrow's network architects to deploy powerful 4G macrocells and 'small cells,' which are built on a common framework."  

Besides using C programming, the company utilizes a new modeling approach for application partitioning and profiling early in the design phase. The inclusion of both an L1 physical layer (PHY) and L2 media access control (MAC) on the same device provides the lowest possible system latency, said Mindspeed. According to the developers, the Transcede 4000 family uses a scalable hardware architecture that enables the same software to be used not only for macrocell, microcell and picocell designs, but also for derivative, low-cost enterprise femtocell designs, as well.

Other key players developing competing solutions include Texas Instruments (News - Alert), Freescale and Tensilica.

Ashok Bindra is a veteran writer and editor with more than 25 years of editorial experience covering RF/wireless technologies, semiconductors and power electronics. To read more of his articles, please visit his columnist page.

Edited by Ed Silverstein