Cadence Design Systems Introduces Open-Source Reference Flow for SoC Verification

Electronic design company Cadence Design Systems Inc., announced plans to use open-source reference flow for verification of system-on-chip using Universal Verification Methodology standard. Engineers will be able to adopt advanced verification techniques where the deployment effort and the risk get minimized and the time-to-market targets can be easily realized.

 

A proven SoC design and UVM compliant test bench components are available as open source as part of UVM Reference Flow 1.0. It is part of the EDA360 strategy to deliver SoC realization capabilities. The users can utilize this to learn and apply advanced verification techniques. They can get hands-on experience for technology usage while running on a UVM-compliant simulator. The users will be able to carry out modifications and observe results after applying different verification scenarios as all the code is provided in clear text form.

 

The Open Verification Methodology (OVM) which Cadence has co-developed has been adopted by Accellera standards organization. Oliver Haller, verification manager at ST Microelectronics stated that the adoption of UVM for verifying their chips has become easier and faster due to the reference flow. They have plans to use this UVM reference flow to demonstrate their methodologies and also for the purpose of internal training.

 

According to Thomas L. Anderson, verification product management director at Cadence, the complexity of chip design for wireless and consumer electronics has gone up considerably and there is pressure on the development teams to apply more effective verification methods and technology. The adoption of advanced techniques has become easier as SoC realization capabilities of EDA360 have been enabled by the UVM Reference Flow. The Design Automation Conference (DAC) scheduled for June 13 to 18 at Anaheim, Calif. is going to showcase UVM Reference Flow 1.0

 

To make productivity management effective, it is necessary to closely integrate design, verification and implementation levels by reducing the productivity gap. EDA360 from Cadence is a step in that direction.

 

In related news, Accent recently released ASMgrid, the industry's first Clean Tech System-on-Chip, or " SoC," platform.