Cadence Design Systems Releases Cadence Encounter Digital Implementation System 9.1

Cadence Design Systems (News - Alert), a dealer in electronic designs, announced that the company’s newly unveiled Cadence Encounter Digital Implementation System 9.1 has all the design, implementation and verification features built into it for developing large-scale, complex SoCs.

 

Cadence has claimed that their Encounter Digital Implementation System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU-enabled design environment for high-capacity, high-performance digital implementation.

 

There is a rising demand for smaller, faster, feature-rich devices from consumers which in turn has increased the need for larger-scale, higher-performance and lower-power SoCs. In order to stay ahead of the competition the semiconductor companies have to go through conflicting design objectives and sometimes incur higher manufacturing costs to offer best and differentiated chip designs.

 

EDI System 9.1 removes these challenges to design productivity through innovative design exploration capabilities. The solution brings together automatic floor-plan synthesis, unique data abstraction modeling, and new concurrent macro- and standard cell placement for users to easily and quickly implement the optimal physical architecture of a chip.

 

Cadence has stated that the new version features new design exploration, integrated signoff/DFM analysis, increased performance and capacity to offer productivity gains and faster time-to-market for multi-million gate SoCs. By supporting RTL synthesis, silicon virtual prototyping, design planning, and full-chip digital implementation and signoff in a single environment, EDI System gives engineers an early, accurate view of design feasibility and allows them to progress immediately to full-scale implementation and final signoff for large-scale, complex designs—without ever leaving the solution environment.

 

Cadence has partnered with major semiconductor companies and ecosystem partners in order to continuously play a pivotal role in driving the definition, development, and enablement for a stream of technology advancements and fundamental shifts in design methodologies and processes, and EDI System 9.1 is a prime example of where it all comes together.

 

David Desharnais, group director of design, implementation and verification product management at Cadence has commented that their partners have provided them with early insight into emerging challenges, and this collaboration is exactly what allowed them to get ahead of the curve. The compounding complexities of chip design and the economics associated with bringing a SoC to market, drive a renewed interest in closing the productivity gap and achieving chip profitability as quickly as possible. The new EDI System 9.1 release provides the industry with the capability to achieve those goals.

 

Recently, NEC (News - Alert) Electronics adopted Cadence EDI and Mitsubishi (News - Alert) selected Cadence Verification Technology.