Cadence, STARC Join to Ensure Optimum Quality in Advanced Chip Design

Cadence Design Systems, Inc. and STARC, the Japan semiconductor industry consortium, have announced a collaboration agreement.

STARC stands for Semiconductor Technology and Academic Research Center and it promotes the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.

The agreement will enable the optimal use of STARC’s regression suites to maintain high quality in electronic design automation software for advanced chip design.

The regression suites and validation flow were developed by STARC and other member companies to qualify EDA software for use by consortium members.

Design engineers are striving to design new complex semiconductor designs in short time intervals. STARC will enable member companies to evaluate and build design flows in less time as it has developed the validation methodology to test new design software when members launch advanced projects, said sources in STARC.

“One of our most important missions is to help our members ensure the quality and accuracy of their chip design software,” said Nobuyuki Nishiguchi, vice president and general manager, Development Department 1 at STARC, in a release. “This methodology allows us to accomplish our mission using tests developed by STARC and the members themselves, thereby ensuring the maximum fit with their requirements.”

STARC has developed common test suites and the methodology includes regression tests for large designs to identify differences between new versions of tools. Test results are stored in STARC’s quality assurance database and reports are sent to STARC member companies.

This process will enable designers to quickly build quality flows according to their requirements. The system now caters to Cadence Conformal Constraint Designer and Encounter Timing System, Encounter Digital Implementation System’s Statistical Static Timing Analysis and Encounter RTL Compiler.

“Mission critical software quality continues to be our number one priority. We’re pleased to work with STARC on the software validation flow with real customer designs,” said Dr. Chi-Ping Hsu, senior vice president of research and development in the Implementation Group at Cadence.

He added that this collaboration will enable Cadence to focus on quality besides ensuring that validation and test results meet designers’ requirements.

Cadence enables global electronic design innovation besides assisting in the creation of integrated circuits and electronics. Cadence software and hardware, methodologies, and services are used by customers to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems.