Berkeley, Solido Collaborate to Enhance Nanometer IC Variation Analysis

Berkeley Design Automation, Inc., a provider of Analog FastSPICE unfied circuit verification platform, and Solido Design Automation reportedly announced a validated flow to reduce variation risk in nanometer designs at the transistor level.

Solido’s Variation Designer will use the AFS Platform to cater to the needs of fabless semiconductor providers. The result is variation analysis capabilities which will help designers to reduce variation risk, said official sources.

The Analog FastSPICE Platform is a unified circuit verification platform suitable for analog, mixed-signal and RF design. It is capable of delivering SPICE accurate results, greater than 10 million-element capacity and comprehensive device noise analysis.

Also the AFS Platform leverages advanced algorithms and numerical analysis for solving the full-circuit matrix and original device equations without shortcuts. The AFS Platform includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis and AFS RF Analysis.

“Rapidly eliminating yield losses due to process variation in nanometer analog, mixed-signal, and RF designs is a key requirement for high-volume nanometer ICs,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. 

“The excellent results from the proven Solido Variation Designer integration with the Berkeley Design Automation AFS Platform will provide our mutual customers a dramatic increase in productivity and design turn-around-time,” he added.

Variation Designer, Solido’s PVT or process, voltage and temperature Corner, Statistical and Proximity applications packages can be deployed for transistor level design. This will consider global, local, environmental and proximity related variation effects. This results in better designs and less variation risk in less time. Variation Designer can be used in the designing of transistors from the PVT corner simulation stage to the statistical analysis stage for finding mismatch effects and yield.

“Variation Designer provides a scalable and extensible solution for solving problems created by process variation in nanometer designs at the transistor level,” said Amit Gupta, president and CEO of Solido Design Automation. 

Gupta added that while using the AFS Platform as the simulation engine in Variation Designer, it is possible to deliver a fast variation analysis and fix capability. This is expected to serve mutual customers of both the companies who will benefit from the enhanced performance of the combined flow.