IC Plus Standardizes Verification Process With Cadence Verification Technology

Cadence Design Systems, Inc., a provider of global electronic design innovation, announced that IC Plus, a communication and networking IC design company in Taiwan, has opted for the Cadence Incisive verification solution with the Open Verification Methodology and Cadence verification IP to optimize development time while simplifying and standardizing its verification process.

 

IC Plus has included the Cadence OVM architecture and methodology into its SystemVerilog verification flow and has been able to reduce its development time from months to only a few weeks. With Cadence solution, IC Plus standardized its verification process, improving production efficiency and predictability and also achieving high-quality verification closure. The OVM, implemented in IEEE (News - Alert) 1800 SystemVerilog, IEEE 1647 e and IEEE 1666 SystemC, is an advanced verification methodology.

 

The OVM defines utilities, a file structure and a verification component architecture that allows to quickly create a verification environment containing reusable components. The SystemVerilog module-based implementation replaces the standard class-based OVM components with module-based components.

 

The OVM, which Cadence co-created, consists of advanced features like interoperability, debugging, reusability and an easy-to-use verification model for testing. Its universal interoperability for SystemVerilog and reusable verification IP help the development and support of multi-language plug-and-play VIP. Debugging and reusability help improve quality, productivity and predictability.

 

“For an IC design company like IC Plus, which has made great investments in R&D, the process of debugging is critical since it affects time and resources during the design process,” stated Albert Liu, R&D Vice President of IC Plus.

 

“With the Cadence solution, we are able to not only set up a complete, automatic and systematic verification flow with less set-up time, but also to discover design bugs in the early stage, which in turn improves the quality of our products,” Liu said.

 

“Today’s IC design companies are striving to improve their design efficiency by simplifying and standardizing their verification processes as early as possible in the design stage,” said Willis Chang, general manager, Taiwan WFO Operations at Cadence. “We are very glad to see IC Plus reaping savings and benefits from Cadence technologies and the Open Verification Methodology. IC Plus is seeing first-hand the capability of the Incisive verification solution for high-performance verification.”