The Cadence Palladium III Accelerator/Emulator has helped Silicon Hive, a global supplier of semiconductor intellectual property (IP), to achieve the highest quality for its HiveGo mobile imaging and video decoding solutions.

 

The solution has made it possible for Silicon Hive to meet IP quality requirements for multi-core, multi-million-gate designs targeting mass-market consumer products. Under the agreement, Palladium transaction-based acceleration (TBA) technology has been integrated into Silicon Hive's development flow.

 

The integration allows the design team to fully validate its RTL IP. This is achieved through TBA that allows the team to run the complete video decoding software on the Palladium system including external system interaction. This technology provides new infrastructure and guidelines to support a reusable accelerated verification environment running at close to emulation speed. For design and verification teams this means reduction of their verification time and increase in productivity.

 

Dr. Jeroen Leijten, CTO at Silicon Hive noted another advantage of Palladium III. It offers full observability of their multi-core hardware, and this allows short iteration cycles in co-debugging hardware and application software.

 

Both companies also said they are looking to extend Silicon Hive's power estimation flow with information provided by the Palladium System. Leijten said this will allow more comprehensive analysis and reduction of the power consumed by complex software applications executed on their HiveGo hardware.

 

"Emerging companies live or die based on the success of their products," said Ran Avinun, marketing group director of system design and verification at Cadence. "Palladium III transaction-based acceleration success at Silicon Hive is another example of our ability to help customers accelerate hardware/software verification for critical projects."

 

In related news, Cadence Design Systems (News - Alert), has announced the release of its system-in-package (SiP) and IC packaging software, the Cadence Allegro 16.3. The solution allows the package designers to play a greater role in co-design and design chain collaboration. It features SiP Layout XL, which puts co-design directly in the package design environment.

 

Cadence’s new co-design technology enables the optimization of designs between packaging and IC design teams. This process doesn’t require packaging designers to learn IC design tools, said the company’s officials.