The CPF-based cadence low-power solution has been integrated into GUC’s PowerMagic methodology to optimize the design of its customers’ complex low-power ASIC implementations in advanced technology.
The Taiwanese foundry integrated the Cadence low-power solution, including cadence encounter rtl compiler, encounter digital implementation system and encounter conformal low power, together with its proprietary in-house tools, into the PowerMagic methodology for design, verification, and implementation.
The integration enabled GUC to develop a complete end-to-end low power ASIC flow, including dynamic voltage frequency scaling techniques. Cadence informs that these techniques facilitate multiple power domains of variable voltages on a single chip in addition to reducing voltage to circuits when peak performance is not required.
The capabilities of the Cadence low-power solution have been benchmarked by their designers who optimized a 65-nanometer, 10-million-gate low power design while correctly implementing more than ten power domains and over 50 power modes, explained C.C. Hsieh, vice president of Design Service at GUC.
Hsieh noted that Cadence has successfully helped GUC resolve low power implementation and verification issues that challenged ASIC designers in a complex low power design project.
Chi-Ping Hsu, senior vice president of digital implementation research and development at Cadence said that this agreement has allowed GUC to deliver a tremendous productivity and quality boost to its design teams aiming to provide superior low-power circuits to its customers.
"The combination should provide tremendous value to GUC's customers."
Cadence is also in
news as
EMA Design Automation’s latest release, EMA (
News -
Alert) TimingDesigner 9.2, interfaces with the Cadence Allegro PCB signal integrity technology.
EMA Design Automation is a major Electronic Design Automation Value Added Resellers. Version 9.2 provides users with a complete SI and timing design environment.
Follow ITEXPO (News - Alert) on Twitter: twitter.com/itexpoAnuradha Shukla is a contributing editor for TMCnet. To read more of Anuradha’s article, please visit her columnist page.Edited by
Jessica Kostek