MEN Micro Inc. has announced availability of the new 32-bit/33-MHz P506 Quad CAN Bus Interface PCI mezzanine card (PMC). This provides four independent, galvanically-isolated controller area network (CAN) interface channels on a single card.
Each interface provides a programmable loop-back mode for self-test operation and signaling and has interrupt capabilities for receiver and transmitter error states, said MEN Micro, a provider of embedded computing and I/O solutions for harsh, mobile and mission-critical industrial applications.
The P506’s interfaces are executed using IP cores inside an onboard FPGA (Field-Programmable Gate Array). Line drivers are implemented on a specialized USM (Universal Submodule) module which can be plugged directly onto the PMC board. MEN Micro’s USM allows updates to a board’s functionality by implementing different IP cores thereby consuming minimum development time.
MEN Micro said that its interfaces can support CAN protocol 2.0A/B with standard or extended data frames from 0 to 8 bytes and a programmable data rate of up to 1Mbps per ISO 11892-1/2. Besides providing support for remote frames under CAN Layer 2 the P506 supports CANopen master and slave. It is also suitable for any PMC-compliant host carrier board in all types of bus systems like cPCI, VME or any standalone SBC.
The new PMC is designed especially to suit mobile and safety critical harsh environments like in industrial control, telecommunications, medical engineering, avionics and other transportation applications. It can function well for a minimum of 10 years and can perform in an extended temperature range of -40 degrees C to +85 degrees C at a maximum of 95 percent RF (non-condensing). Additional protection can be provided against dust and humidity with conformal coating, the company claims in a release.
According to the specifications given by MEN Micro, the unit is rated to withstand shock at 15 g/11 ms, bumps up to 10 g/16 ms and sinusoidal vibration of 1 g/10 Hz to 150 Hz. EMC (
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Alert) protection conforms to EN 55022 for radio disturbance, IEC1000-4-2 for electrostatic discharge (ESD) and IEC1000-4-4 for electrical fast transient/burst testing.
The FPGA controls the P506’s 32 MB of soldered SDRAM memory and 2 MB of non-volatile Flash memory for FPGA data and the Nios firmware. Connections are made at the periphery through the front panel on a shielded 50-pin HP D-Sub SCSI2 receptacle connector.
Shamila Janakiraman is a contributing editor for TMCnet. To read more of Shamila’s articles, please visit her columnist page.Edited by
Patrick Barnard