Gennum's Snowbush IP Group Develops Integrated PCI Express 3.0, Controller IP Solution

Gennum Corp. has announced that its Snowbush IP group has developed the industry's first available integrated PCI Express 3.0 (Gen 3) PHY and Controller IP solution.

Ewald Liess, general manager of the Snowbush IP group at Gennum, said that PCIe 3.0 IP is critical for the development of next-generation computing products.

PCIe 3.0 opens up more bandwidth using the same physical connectors. In addition, it adds new features to improve the user experience in server network and computer products using PCI Express, said company officials.

This latest offering is architected for low power and area on both the PHY and Data Link layer. Officials said that it features low power consumption from a proprietary 5-tap Decision Feedback Equalization (DFE) and H-bridge transmit driver.

The footprint of PHY silicon is small and includes I/Os, ESD structures, and PCS Layer, in 1-, 2-, 3-, and 4-lane configurations. Officials said that each lane of the PHY can be configured to operate in Gen 1, Gen 2, or Gen 3 mode, and multiple 4-lane PHYs can be configured as x8, x16, x32, and greater links.

Additionally, the Controller features low latency pipelined architecture. Officials said that the Controller's micro and macro power options deliver a low energy profile that compliments the PHY layer's low power consumption.

The integrated Snowbush device PHY and Controller solution satisfies the 8 GT/s speed requirement of PCIe 3.0, said officials.

"PCI Express 3.0 doubles the effective throughput of the existing 2.0 standard, meeting many of the future throughput needs of interface chips for servers, communications, and enterprise storage devices," said Jag Bolaria, senior analyst at the Linley Group.

He anticipated that this new standard will begin to see deployment in 2010, adding that Snowbush now has both the PHY and Controller, allowing PCIe 3.0 market movers a cost-effective way to deploy products based on this standard.

The new Snowbush PHY IP block employs a variety of techniques such a proprietary dual-loop hybrid clock-and-data recovery (CDR) architecture which recovers the clock with less jitter; internal voltage and current regulation for sensitive circuits; fully differential circuitry and clock signalling.

In addition, it also employs a coupled ring oscillator VCO design with jitter performance usually only found in complex LC tank oscillators; and extensive use of guard rings within the macro.

According to company officials, some of the new Controller IP block features are atomic operation; address translation services; transaction-Layer Processing Hints (TPH); 5.0 GT/s and 8.0 GT/s speed negotiation; and more.

The new PCIe 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies. Officials said that this enables early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8.0 Gigatransfers per second (GT/s) performance of this new PCI-SIG standard.

The Snowbush integrated PHY and Controller PCIe 3.0 IP is now available for licensing in TSMC 40nm and below, and can be ported to other foundries.