Sequans Powers SQN1210 Chip with Cadence Low-Power Solution

Looking to use some effective power saving techniques in its chips, Sequans Communications reportedly has selected a low-power solution from Cadence. The company will implement these solutions in its newest 65-nanometer Mobile WiMAX (News - Alert) baseband and RF single die chip, the SQN1210.

 

Companies are fast realizing that managing power is essential when it comes to designing new applications. In addition to timing and area, power has emerged as a primary design constraint in creating a wireless application for consumer electronics. Now, a WiMAX application must simultaneously consider all design constraints (including power) to succeed in the market.

 

The SQN1210 offers more area savings for system integrators as it integrates baseband and triple band RF into a single die. The chip is capable of operating at 600MHz and its total power drops to less than 0.5mW during the standby mode. The Cadence Low-Power Solution contributed to these innovative low power achievements.

 

“Sequans’ tremendous success is a tribute, in part, to the efficiency of the Cadence Low-Power Solution and the Cadence Design Services team,” said Steve Carlson, vice president of Low-Power Solutions at Cadence. “The Sequans tapeout experience demonstrates that the Cadence Low-Power Solution delivers on rigorous power budgets, while improving design efficiency.”

 

Sequans used the complete CPF-enabled Cadence Low-Power Solution for this project. This includes the Incisive Enterprise Simulator, Encounter Conformal Low Power, Encounter RTL Compiler and Encounter Digital Implementation System. For this design, Cadence Design Services provided expertise on physical implementation and signoff power analysis. Cadence Design Services was also able to provide real-time signoff power analysis during implementation using the integrated signoff power analysis capabilities in the Encounter Digital Implementation System.

 

Recently, the company improved its Cadence Low-Power Solution to support new on-chip power management schemes enabled by the recently ratified Si2 Common Power format Version 1.1. Apart from Incisive functional verification, system design and verification technologies, the enhanced solution will include Cadence Encounter digital implementation and logic design technologies. Now, designers can use the upgraded solution for accurately modeling, analyzing and debugging power management components which can integrate into large system-on-chip designs.