Azuro Intros New Clock Concurrent Optimization Tool

Azuro, a provider of software tools for semiconductor chip design, has announced a new clock concurrent optimization tool named Rubix.

 

The revolutionary new tool can deliver up to 20 percent increase in chip speed and reduces chip time to market by combining the separate design flow steps of physical optimization and clock tree synthesis (CTS (News - Alert)).

 

David Dumolin, director engineering at NVIDIA, finds Rubix very useful as it plugged easily into their flow, and improved key chip speed metrics (WNS and TNS (News - Alert)) out of the box on some of their toughest blocks. He is also pleased with the fact that it did not impact the area.

 

“We view clock concurrent optimization as a key evolutionary step in backend physical design,” he added.

 

Azuro cites physical optimization as the crucial step in the design flow which most influences chip speed, area, and power. This step occurs before clocks are inserted into a design during the clock tree synthesis step and makes decisions based on an idealized, balanced model of clocks. According to officials, this model has diverged dramatically from reality due to design complexity, on-chip-variation, and low power.

 

Because this divergence directly impacts the validity of decisions made during physical optimization, it degrades achievable chip speed and results in a dramatic spike in manual iterations in design flows. Clock concurrent optimization builds clocks during physical optimization and therefore makes all decisions based on real clocks, not idealized clocks.

 

“Clock gating, on-chip variation, and an explosion in inter-clock timing complexity collectively cripple the ability of traditional physical optimization tools to perform timing optimization effectively,” said Greg Buchner, former vice president engineering at ATI Technologies (News - Alert) and AMD, and an advisor to Azuro.

 

Buchner sees clock concurrent optimization as something fresh and much needed by the chip design community.

 

Noting that traditional clock tree synthesis died at 65nm, EDA industry analyst, Gary Smith, chief analyst at GSEDA sees the logic behind merging clock tree synthesis and physical optimization.

 

The clock concurrent optimization builds clocks simultaneously with optimizing logic, and thus the time available for logic functions can be varied by individually controlling when clock signals arrive at registers. Thanks to clock concurrent optimization, chip speed becomes limited by whichever “chain” of logic functions is slowest. These chains break only when they reach an input to, or an output from, a chip or when they loop back on themselves.

 

“Clock concurrent optimization is the right way to address the crippling pre- to post-CTS timing gap which has emerged in design flows today,” said Paul Cunningham, Azuro’s co-founder and CEO. “We feel privileged to be able to introduce a technology concept as fundamental as clock concurrent optimization, and look forward to helping chip design teams exploit the significant benefits Rubix can offer to their businesses.”