Taiwanese IC Design Company Selects Cadence Test Solution

Moai Electronics, an IC design company in Taiwan, has deployed the Cadence Encounter RTL Compiler and Encounter Test solution for a flash memory controller with dramatically faster time to market, lower test costs, and higher quality.

 

Both Encounter RTL Compiler and Encounter Test are key components of the Cadence Logic Design Team Solution and digital implementation user segments. The environment provides a complete one-pass global logic-test synthesis flow and access to all DFT functionality, including Memory BIST, test point insertion, multiple compression architectures, and sophisticated masking for compression.

 

Cadence Design Systems’ (News - Alert) officials cite other core strengths of this integrated flow including an ultra-fast DFT rule checker with RTL feedback, power-aware scan synthesis and ATPG solution, and physically-aware scan synthesis.

 

Moai's design team leveraged the Encounter RTL Compiler global synthesis and Encounter Test to improve the RTL to ATPG turnaround time from weeks to days. The single flow for logic and DFT synthesis provided several benefits such as greater design optimization, ease of use, and increased productivity.

 

The company’s officials explain that the advanced fault modeling capability and flexible compression strategy provided higher quality while meeting aggressive tester pin-count cost goals.

 

Encounter RTL Compiler and Encounter Test enabled the Taiwanese Company to reduce test data volume and test application time, and achieve better timing convergence during physical implementation, according to P. F. Lin, president of Moai Electronics. This outstanding result enabled increased quality for the end product, and Lin said that this is solid proof of the value of Cadence’s highly integrated design and test environment.

 

Lung Chu, president of Asia Pacific for Cadence Design Systems pointed out that Moai has seen first-hand how Cadence Encounter RTL Compiler and Encounter Test technologies can enhance flash memory controller design.