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May 08, 2013

Invarian Develops Full-Chip Signoff Analysis for Complex Integrated Circuits

Invarian, Inc., a provider of full-chip concurrent signoff analysis solutions for complex integrated circuit (IC) designs, has developed advanced algorithms for fast and accurate full-chip analysis for large capacity designs. The R&D team takes care of analog and digital designs with concurrent analysis of power, signal timing, electromigration, voltage, temperature and packaging parameters.

Invarian delivers a suite of tools devised for accurate and effective analysis of designs from block level to chip level designs. The patented concurrent methodologies allows users the benefit of physical measurement accuracies without delays in runtime, yet also offers the ability of handling extremely large design files.

Full-chip IR-drop and electromigration have traditionally been a bottleneck for physical verification within the EDA industry. Invarian’s hierarchical methodology allows the semiconductor industry the ability to overcome that hurdle and more accurately model full-chip analysis for IR-Drop, electromigration and power across all process nodes, including 20nm and FinFET.

Invarian’s solution utilizes only industry standard design file formats and creates a path for users to quickly learn the platform in a user-friendly environment designed for quick turnaround times.

Earlier generation physical design tools were inaccurate, which led to expensive re-spins. Verification takes overall signoff high turnaround time. Designs are complex and simulation capacity is only few clock cycles. The proliferation of point tools involved in sign-off analysis provides ambiguous results. Also, stand-alone tools are difficult to integrate into an existing flow.

Accurate IC signoff results are achieved with concurrent analysis of all parameters. Without concurrent analysis, lack of correlation between simulated and real-life IC behavior causes severe tape-out problems. Invarian technology detects problems that are usually detected after manufacturing; sign-off results correlate with real physical measurements within two percent.

“Accuracy is key for signoff analysis,” stated Alex Samoylov, COO, vice president of engineering and co-founder of Invarian.  “The methodology we have devised does not use predefined corners for analysis. Sign-off analysis is performed in the simulation environment that represents real-life conditions. And we have the only tools on the market that implement concurrent analysis of parameters affecting the accuracy of sign-off data.”

One of Invarian’s major advantages compared to existing solutions is the new methodology created by the company’s R&D team in Moscow and Silicon Valley.

“Fast adaptation of Invarian’s revolutionizing solutions at some of the world’s leading processor, switch and mobile companies underlines how well Invarian’s tools are designed for engineers who require fast, accurate results from gate level through to the 3D package environment,” commented Invarian CEO Jens Andersen.

“The strength of our combined experience and the proven expertise of the R&D team and executives helps our customers to achieve results that correlate with physical reality and is the best bet for first time silicon success increasing overall ROI,” Andersen continues.

Edited by Rachel Ramsey

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