infoTECH Feature

April 17, 2013

Green Hills Software Upgrades TimeMachine Trace Tools

Green Hills Software recently announced that its suite of TimeMachine Trace Tools now includes broad multicore enhancements. With Multicore TimeMachine support, MIPS and Renesas RH850 and V850 processors will now have increased visibility into complex software running on multicore. The result is improved time-to-market and reliability of multicore-based firmware products.

For SoC designers, multicore TimeMachine will enhance the pre-tape-out chip verification, bring down risk, improve time-to-market, and speed-up silicon sales. With advanced scripting options, TimeMachine will also be able to support automated testing over virtual platforms.

Tony King-Smith, executive vice president of marketing, Imagination Technologies (News - Alert) said, "Imagination is delighted that our long-time partner Green Hills is making its multicore TimeMachine tools available for MIPS CPUs. Multicore and multi-threaded MIPS cores provide high-performance, efficient processing across a wide range of embedded and consumer products. With multicore TimeMachine, developers creating software for these processors have a new level of visibility and control, with the ability to debug, optimize, and test code in powerful new ways.”

Multicore TimeMachine will provide developers with the ability to visualize, replay, and debug the execution of their software backward in time spanning a number of cores within a SoC. The TimeMachine suite will also enable firmware engineers to locate bugs and improve the efficiency of their multicore systems. With the inclusion of trace-based visibility within the TimeMachine, complex interactions that take place between multiple heterogeneous cores will be easier to see. This in turn will help in reducing the turn-around on locating software defects.

With the TimeMachine debugger users can also align the movement of all cores, and they will be able to create software and hardware breakpoints, which will result in all cores stopping together as soon as they hit the breakpoint. This will allow the user to view the running of all cores before and upon hitting those breakpoints.

Edited by Stefania Viscusi

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