Cadence Design Systems (News - Alert), Inc. has successfully accomplished verification projects for several major clients with the help of Cadence Verification IP (VIP) for ARM (News - Alert) AMBA protocols. Major clients of Cadence like CEVA, Inc., Faraday Technology Corporation, and HiSilicon Technologies Co., Ltd. have now been able to shorten their verification timings to weeks. As a unit of Cadence’s wide-ranging VIP Catalog for SoC verification, these organizations have deployed the extremely sophisticated ARM technology with the assistance Cadence VIP for AMBA protocols.
Cadence, in association with ARM, has guaranteed the compatibility of VIP offerings with ARM CoreLink CCI-400 Cache Coherent Interconnect and CoreLink NIC (News - Alert)-400 Network Interconnect with the assistance of AMBA 4 protocols. An established, flexible and extremely distinguished verification offering for ARM CoreLink interconnect IP can therefore be advantageously used by common ARM and Cadence users.
In a statement, Joe Convey, director of Design Enablement at ARM, said, "As the complexity of ARM partners' designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence verification IP solution for AMBA protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology. ARM's partnership with Cadence helps customers achieve continued success as they roll out next-generation designs incorporating our most advanced AMBA specifications such as AXI4 and AXI Coherency Extensions."
According to Ting Lei, Director, Cloud Computing Department at HiSilicon, the organization can now offer defect-free SoC designs in a rapid and competent manner with the Cadence VIP for AXI4 and ACE.
Richard Kingston, director of Marketing and Investor relations at CEVA (News - Alert), said, "CEVA is the world's leading licensor of DSP cores and platform solutions for the mobile, digital home, and networking markets. Our proprietary FIC (News - Alert) bus delivers the right balance of features needed to deliver optimized designs. The flexible Cadence VIP for AXI gives us the ability to adapt it to our unique application and exhaustively verify the bus interconnects. This cut our verification effort from six months to three weeks."
According to Ken Liao, AVP, RD at Faraday, the organization implemented the Cadence VIP solution mainly for its development, complete-feature set and assistance, ensuring all-inclusive SoC and IP level verification coverage to customers.