Cadence Unveils Enhanced Allegro Package Designer, SiP Layout

Cadence Design Systems (News - Alert), Inc. has unveiled an enhanced version of its Allegro 16.6 Package Designer and System-in-Package offering. Discreet IC package necessities for next-generation smartphones, tablets, and ultra-thin notebook PCs are supported by Allegro Package Designer.

The latest release, version 16.6 of Allegro Package Designer and Cadence SiP Layout comprises of open cavity support for die position. The latest release, with its latest wirebond application mode, offers enhanced competence. An extremely all-inclusive design and analysis offering for IC package design in the industry is offered by this release through its wafer-level-chip-scale-package or WLCSP capability.

In a statement, Choon Heung Lee, Corporate VP of Product Management at Amkor (News - Alert) said, "The increasing demand for high-end and next-generation IC package designs is driving us to use innovative design tools and techniques to meet our customers' needs. Based on our testing of Allegro Package Designer and Cadence SiP layout, we expect Cadence's IC package design solutions to help us meet the growing list of challenges in advanced package design."

The issues related with IC package deployment for small/thin customer electronics offerings have been resolved by Cadence by incorporating associated functionality into its Allegro tools. A fresh database object for open cavity placement is supported by Allegro 16.6 offering, ensuring improved capabilities like DRC and 3-D viewing for allowing die placement inside a cavity of the package substrate.

Throughput is considerably enhanced with the addition of a sensitive wirebond application, which concentrates completely on the wirebond process. An extremely proficient WLCSP flow is ensured by the Cadence Allegro suite as it reads and writes GDSII data in an extremely brief manner. The substrate-level interconnect deployment of a package is considerably hastened with the latest sophisticated package router, which uses Sigrity technology.

Keith Felton, Director of Product Marketing Group for PCB and IC Packaging at Cadence said, "The design challenges of small/thin consumer electronics products continue to drive the advancement of the Cadence leading package design tools. In addition to offering IC package solutions with a physical design perspective, Allegro now enables customers to analyze and validate high-performance, low-power devices for electrical compliance as well. This improves design time and speeds time to market."