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October 09, 2012

Cadence Signoff Solutions Benefits STMicroelectronics

Cadence Design Systems (News - Alert), Inc., a company that provides global electronic design innovation, recently announced that its signoff solutions have benefited STMicroelectronics (News - Alert), a semiconductor provider serving customers across the spectrum of electronics applications.

With signoff solutions from Cadence, STMicroelectronics has been able to reduce multiple weeks from its design schedule on a 28-nanometer system-on-chip (SoC) meanwhile accelerating time to market in the tapeout of an advanced SoC. STMicroelectronics used Cadence Encounter Timing System with Cadence QRC Extraction in conjunction with Encounter Digital Implementation (EDI) System.

Encounter Timing System is a full-chip static timing analysis (STA) solution providing gate-level delay calculation, signoff-level timing and signal integrity (SI) analysis, statistical timing and leakage analysis, advanced on-chip variation analysis and advanced node functionality required for double-patterning and waveform effects.

On the other hand, Cadence QRC Extraction is an integrated extraction solution for design implementation and validation at 90nm and below. Cadence Encounter Digital Implementation (EDI) System provides the most effective methodology to maximize performance and minimize area and power for high-performance, giga-scale designs.

"The Cadence signoff solution cut weeks off our development schedule," said Thierry Bauchon, R&D director for STMicroelectronics' Unified Platform Division. "In one 24-hour period, for instance, we were able to fix thousands of hold violations across more than 60 mode-corner combinations on this design, which contained more than 20 million cells -- something that would have taken us weeks to close with our prior signoff technology." 

"We are passionate about collaborating with technology innovators like ST, and are committed to continuing to deliver the best and most productive technology, tools, and flows to help them get their jobs done," said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "For complex, MMMC, 28-nanometer design and ECOs, the integrated Cadence signoff solution continues to impress customers with its unique ability to help deliver superior quality of silicon, designer productivity, and accelerated time to market."




Edited by Rachel Ramsey
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