Xilinx Showcases QPI 1.1 Interface with FPGAs

The 7 Series All Programmable FPGA family from Xilinx (News - Alert) offers breakout performance, capacity, and system integration and is built on the state-of-the-art 28nm HPL process technology. It also enhances price/performance/watt.

Recently, the company announced that it will demonstrate a field programmable gate array (FPGA) interfacing to an Intel (News - Alert) Sandy Bridge Xeon Processor using the QuickPath Interconnect (QPI) protocol at an upcoming event.

Xilinx’s QPI solution offers developers a low-latency, high-performance link to Intel Xeon Processors from Xilinx All Programmable FPGAs. By using Xilinx FPGAs high performance processing and flexible I/O capabilities, this solution provides the best possible overall system performance and power consumption.

With the help of the Xilinx QPI development platform complete with IP core and a development module designed to plug directly into an existing Intel Sandy Bridge CPU socket, hardware designers can start developing a QPI-based solution. The QPI 1.1 full width link between the Xilinx Virtex-7 FPGA and the Intel Sandy Bridge CPU functions at 6.4 Gb/s per lane over 20 lanes, the company stated in a statement.

“With today’s demonstration, Xilinx now has the first FPGA-based low-latency, high-bandwidth interconnect intellectual property (IP) core for Intel Xeon processor-based systems,” said Nick Possley, senior director of wired communications at Xilinx. “This means Xilinx solutions can now play a major role in reducing CAPEX and OPEX (News - Alert) for Data Centers by enabling higher compute performance within a given server form factor either by directly accelerating applications or offloading I/O intensive operations.”

Recently, the company partnered with Barco Silex, a certified Xilinx Alliance Program member, to unveil a platform that integrates hardware-validated IP, reference designs and system integration services.

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