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June 09, 2011

Arteris Announces Support for the Second Phase of AMBA 4 Specification

Arteris has announced its support for AMBA 4 ACE, the second phase of the AMBA 4 specification. To the deployment of new AMBA 4, the company has contributed technologies such as virtual memory and memory barriers.

Calling Arteris an active participant in the AMBA 4 specification process, Michael Dimelow, director of marketing for Processor (News - Alert) Division at ARM, said that his company is partnering with Arteris to ensure the swift deployment of critical new computer science techniques introduced with AMBA 4 ACE, such as memory barriers and distributed virtual memory.

“This will provide joint customers with a solution to help design high performance heterogeneous multicore SoCs by utilizing a combination of the ARM CoreLink CCI (News - Alert)-400 cache coherent interconnect and the Arteris FlexNoC interconnect,” Dimelow said.

San Jose, California based Arteris provides network-on-chip (NoC) interconnect IP and tools to accelerate system-on-chip semiconductor (SoC) assembly for a wide range of applications.

“Arteris has benefited from its interconnect ecosystem partnership with ARM (News - Alert) to deliver high quality interoperability to ARM IP in timely manner,” said Charlie Janac, president and CEO Arteris.

Janac said that the company has achieved its goal of offering an interconnect solution that accelerates customer adoption of the latest ARM processor cores like the ARM Cortex A15 MPCore together with the Arteris FlexNoC interconnect and interchip link products.

Arteris, recently, also announced that its NoC interconnect IP and tools will be available to TSMC customers as part of TSMC Reference Flow 12.0, the foundry's latest design reference flow to enable its advanced 28nm (nanometer) process technology.

Anshu Shrivastava is a contributing editor for TMCnet. To read more of Anshu’s articles, please visit her columnist page.

Edited by Rich Steeves

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