Cadence Partners with TSMC on New 28-Nanometer Flows

EDA vendor Cadence Design Systems has further tightened its collaboration with Taiwan Semiconductor (News - Alert) Manufacturing Company (TSMC), by signing a new partnership deal and unveiling an array of new technologies incorporated into the new TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 that ensure 28-nanometer production readiness.

"The EDA360 vision calls on key industry players to work collaboratively to solve growing design complexity challenges," Dave Desharnais, group director, product marketing, Silicon Realization at Cadence said in a press release.

"Our close relationship with TSMC enables us to pioneer AMS, ESL, 3D-IC and DFM solutions that are critical to the productivity and predictability of SoC design at advanced nodes. Together, we ensure customers can accelerate their 28-nm designs and successfully get them into high-volume production," Desharnair added.

As indicated, TSMC and Cadence have partnered in the areas of electronic system level (ESL), 3D-IC implementation, design for manufacturing (DFM), and analog mixed-signal (AMS) design.

Support for the new flows enables customers to address the complex challenges of low-power digital, analog and mixed-signal design for wireless, networking, consumer and other applications. By collaborating with TSMC to deliver these new flows, Cadence believes that it can continue providing the industry with holistic, end-to-end design solutions -- a key requirement for delivering on the EDA360 vision.

"Our new reference flows reflect significant technological advances that result from close collaboration with industry leaders like Cadence," said Suk Lee, director of Design Infrastructure Marketing at TSMC.

"The combination of Cadence end-to-end solutions with our new design methodologies ensures that designers can further accelerate the development of 28-nanometer designs," Lee added.

The ESL capabilities, delivered as part of TSMC Reference Flow 12, are developed by Cadence and enabled by the Cadence System Development Suite announced last month. The suite features four connected platforms that enable hardware-software co-design from architectural-level development through to prototyping.

The combination of the TSMC Reference Flow 12 with the Cadence System Development Suite is said to support SoC virtual prototyping for TLM and TLM/RTL platforms, early software development using the open SystemC language, and advanced functional verification. In addition, the reference flow scales to support 28-nm development with a link to the TSMC iPPA power estimation tool, giving users the ability to better estimate the overall power consumption of their system and make early architectural decisions to optimize power.

Reference Flow 12 also leverages new 3D-IC technology developed by Cadence and imec to automate production testing of 3D stacked ICs and through-silicon vias (TSVs). Additional Cadence contributions to the flow include 3D-IC support for a digital implementation flow, with static timing analysis, IR analysis, and thermal analysis, along with RC extraction and physical verification production flows.

Cadence and TSMC have also been working closely together to add circuit optimization, sensitivity analysis for layout dependent effects (LDE), LDE-aware layout, device reliability analysis and multi-technology simulation (MTS (News - Alert)) to the AMS reference flow to produce AMS Reference Flow 2.0.