Silicon Laboratories Introduced Integrated Clock ICs for OTN

Silicon Laboratories (News - Alert) Inc., a company in analog-intensive, mixed-signal ICs, introduced integrated clock ICs to address the complex timing requirements of high-speed optical transport network (OTN) applications.

By making use of Silicon Labs' patented DSPLL technology, the new Si5374 and Si5375 clocks are said to be the first single-chip timing ICs, integrating four independent, high-performance phase locked loops PLLs, providing twice the PLL integration and 40 percent lower jitter than competing solutions

Being a next-generation protocol (ITU G.8251 and G.709) that provides an efficient way to multiplex different services onto optical networks, OTN provides good support for edge routers, wavelength division multiplexing (WDM) transmission equipment, Carrier Ethernet and multi-service platforms. OTN applications require multiple low-jitter clocks at non-integer-related frequencies; they pose complex timing challenges. Silicon Labs' quad-DSPLL Si537x devices produce up to eight low-jitter output clocks. They simplify the design of any-protocol, any-port 10G, 40G and 100G OTN line cards.

Each DSPLL clock multiplier can be configured to generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input. It provides the exceptional frequency flexibility to minimize the need for multiple jitter-cleaning clock ICs. The Si537x devices provide flexible DSPLL architecture to simplify the generation of high-speed PHY reference clocks with jitter performance of 0.4 picoseconds. It eliminates the need for discrete VCXO-based PLLs currently used in OTU3 and OTU4 applications.

The Si537x devices can reliably lock to gapped clock inputs while gapped clock inputs are a critical OTN line card clock requirement without separate upstream low-bandwidth PLLs. Other features, including SONET-compatible jitter peaking (0.1 dB max) and an innovative hitless switching capability that minimizes output clock phase transients during reference switching, also come with these devices. They produce a 25x smaller phase transient than competing solutions. Featuring a fully integrated loop filter that supports user-programmable bandwidths as low as 4 Hz, each DSPLL engine enables wander filtering and jitter attenuation, configurable on a per channel basis.

The Si5374 device has eight input clocks and eight output clocks. The Si5375 offers four input clocks and four output clocks for applications requiring fewer clocks. This device is designed with its quad-DSPLL configuration. Its single Si5374 clock can generate different frequencies simultaneously, enabling the design to support SONET/SDH, 1/10/100G Ethernet, 1/2/4/8/10G Fiber Channel, 3G/HD SDI video and other protocols simultaneously in the same device.

The Si537x clocks come with a smooth upgrade path. Existing customers can migrate from Silicon Labs' Si5319/26 jitter-attenuating clocks to a more integrated jitter-cleaning clock solution. They effectively replace four timing devices with a single IC in high-port-count 10G/40G/100G OTN line cards.

Samples and production quantities of the Si537x clock ICs are available now. Si537x clock prices range from $39 to $59 in 10,000-unit quantities. The Si5374-EVB and Si5375-EVB evaluation kits are available for $350 each. (All prices are in USD.)

In related news, Silicon Laboratories Inc. reported a seven percent sequential increase in first quarter revenue to $119.6 million due to strength in its broadcast and broad-based product lines.

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