STATS ChipPAC Expands TSV Capabilities

STATS (News - Alert) ChipPAC Ltd., a provider of semiconductor test and advanced packaging services, expanded its 300mm Through Silicon Via (TSV) offering with the addition of mid-end manufacturing capabilities.

“The driving demand behind 3D integration is the need to scale semiconductor devices to smaller and smaller geometries with higher input/output (I/O) requirements. STATS ChipPAC is enabling advancements in 3D packaging with the development and qualification of key technologies that support TSV solutions,” Han Byung Joon, executive vice president and chief technology officer at STATS ChipPAC said in a press release.

“We have had the capability to fabricate, assemble and test TSV interposers for four years and believe the timing is right to invest in 300mm mid-end TSV manufacturing for our customers,” Joon added.

Through Silicon Via, or the TSV, is noted to be an important developing technology that utilizes short vertical interconnections through a silicon wafer to achieve greater space efficiencies and higher interconnect densities than wire bonding and flip chip stacking. When combined with microbump bonding and advanced flip chip technology, TSV technology is said to offer a higher level of functional integration and performance in a smaller form factor.

STATS ChipPAC claims that it is one of the first Outsourced Semiconductor Assembly and Test (OSAT) providers to invest in TSV technology with a 51,000 square foot research and development facility dedicated to the development of next generation wafer level integration with TSV technology.

STATS ChipPAC has complete front to back-end manufacturing capabilities for 200mm wafers and currently handles both chip-to-chip and chip-to-wafer assembly for TSV technology. This includes high density microbump capabilities in both solder and copper column materials, microbump bonding down to 40um pitch, thin wafer handling, wafer level underfill, thin wafer dicing and microbumps for flip chip interconnection. Microbump technology is critical to delivering fine pitch, low profile solutions for high performance devices.

Recently STATS ChipPAC made the addition of a 300mm “mid-end” process flow that occurs between the wafer fabrication and back-end assembly process. Mid-end processes is said to support the advanced manufacturing requirements of 2.5D and 3D TSV as well as wafer level packaging, flip chip and embedded die technology.

TMC (News - Alert) also reported recently that STATS ChipPAC has received Analog Devices (News - Alert), Inc.'s “Supplier Excellence Award” for Contracted Production. This is the third consecutive year that STATS ChipPAC has received ADI's Supplier Excellence Award for providing full turnkey packaging and test services.