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January 13, 2011

GlobalFoundries Unveils Industry's First 28 nm Digital Design Flows

Full-service semiconductor foundry GlobalFoundries unwrapped the industry’s first 28 nm silicon-validated signoff-ready digital design flows to help chip designers deliver the next generation electronic devices for power-sensitive mobile and consumer applications.

Developed in collaboration with EDA/IP ecosystem leaders and based on the foundry’s 28 nm super low power (SLP) technology with gate first high-k metal gate (HKMG), the flows are precisely tuned to help overcome the unique challenges of designing and manufacturing integrated circuits at leading edge nodes.

The new signoff-ready flows were developed with recognition of the need for silicon validation to ensure first-time-right silicon success, setting a new standard for quality, scope, and relevance in foundry flows. Customers can now produce signoff ready 28 nm designs using the industry’s most advanced set of synthesis, place and route, sign-off, and DFM tools, tool scripts, and methodologies, said the foundry service provider.

“Many of the world’s top IC designers are using our 28 nm technology to deliver tomorrow’s most innovative mobile and consumer devices,” said Mojy Chian, senior vice president of design enablement at GlobalFoundries.

He added, “By collaborating closely with our partners in the EDA/IP ecosystem to provide a comprehensive 28 nm design platform, we are giving customers confidence that their designs will be brought to life smoothly and in time to meet their critical market requirements.”

Traditional foundry design flows have not taken into account the growing interaction of design and manufacturing at advanced technology nodes. GlobalFoundries has addressed these issues by emphasizing early collaborative development with providers of EDA software and IP to validate design methodologies against real silicon, according to manufacturer.

In addition to tight integration with the foundry’s signoff physical verification solution, all flows leverage GlobalFoundries’ heritage as a leader in Design-for-Manufacturing (DFM) by supporting DRC+, the company’s silicon-validated solution that goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable up to a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy, said GlobalFoundries.

EDA partners include Cadence, Synopsys (News - Alert), Mentor Graphics, Magma and Apache Design Solutions. With Cadence, it has jointly developed a complex 28 nm-SLP design that fully demonstrates Cadence’s portfolio of advanced silicon implementation tools, including high-level synthesis, low power, routing, DFM, and verification.

Likewise, with Synopsys,  the two have collaborated to develop a 28 nm-SLP design flow based on the Synopsys Galaxy Implementation Platform, along with a 28 nm-SLP Foundry-Ready System technology plug-in for the Lynx Design System.

 GlobalFoundries and Mentor Graphics are developing a complete reference flow based on the Olympus-SoC and Calibre InRoute products. The Olympus-SoC router has been qualified for GlobalFoundries’ 28 nm-SLP technology, providing support for both advanced 28 nm ground rules and recommended rules to implement DFM, improved recipes for efficient routing, and support for manufacturing scoring analysis.

Similarly, the company has worked with Magma to develop a 28 nm-SLP signoff-ready flow based on the Talus Vortex IC implementation platform. And is jointly developing a 28 nm-SLP signoff-ready flow with Apache Design Solutions using RedHawk and Totem to provide a robust solution to meet low power demands.

Ashok Bindra is a veteran writer and editor with more than 25 years of editorial experience covering RF/wireless technologies, semiconductors and power electronics. To read more of his articles, please visit his columnist page.

Edited by Janice McDuffee

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