infoTECH Feature

March 30, 2010

EnSilica Announces Latest eSi-RISC Development Suite Version 2.1

EnSilica, a provider of front-end IC design services, has announced the launch of latest version of its eSi-RISC Development Suite, a platform for easy evaluation of the company’s eSi-RISC processor family along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.

The eSi-RISC is a family of highly configurable and low-power soft processor cores. The family encompasses the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSI-3250 32 bit processor and eSi-3250sfp incorporating a single precision floating point processor. This family features highly pipelined nature that provides customers with a technology-independent solution that is ideal for both FPGA applications and ASIC technologies.

EnSilica’s new eSi-RISC Development Suite v2.1 encompasses a new hardware evaluation platform based on Altera (News - Alert)'s Cyclone III FPGA. The Development Suite also offers rapid software development and debugging features. This was possible due to Eclipse IDE (Integrated Development Environment) and industry-standard GNU GCC 4.4.0 toolchain, which now features native support for the eSi-RISC architectural features.

According to a press release, the FPGA configurations are provided for the complete eSi-RISC processor family, along with numerous application examples that demonstrate how the system-on-chip peripherals could be used, such as a full port of the open source FreeRTOS with lwIP TCP/IP network stack.

Apart from providing comprehensive documentation as well as a range of interactive tutorials, the eSi-RISC Development Suite v2.1 that features extensive debug facilities helps in improving the development productivity considerably. In addition, the non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger that provides the ability to examine data, insert break and watch points and control program execution, thereby offering developers with full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly.

Developers leveraging eSi-RISC Development Suite v2.1 can also debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics (News - Alert)' ModelSim from the Eclipse GDB project debugger through a network socket connection. The ModelSim displays disassembled instructions as text in the wave display. This feature is helpful for SoC level hardware and software debugging, said officials in the release.

The WinPcap has been integrated into the new eSi-RISC Development Suite's Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. With this, the network application debugging is considerably simplified, EnSilica said.

Ian Lankshear, managing director of EnSilica, said, 'The ease and speed with which processors can be evaluated and applications developed and tested, plays an important role in developers' choice of processors.'

Lankshear added, 'The eSi-RISC Development Suite v2.1 includes a host of new features and capabilities to enable our eSi-RISC processor family to be easily evaluated and quickly deployed.'

Jayashree Adkoli is a contributing editor for TMCnet. To read more of Jayashree's articles, please visit her columnist page.

Edited by Patrick Barnard

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