Panasonic and Renesas Technology Announce Joint Venture

Panasonic (News - Alert) Corporation and Renesas Technology recently announced their latest joint venture in the field of technology development. The two companies plan to work together on the System–on-a-chip (SoCs) of the next generation 32-nm (nanometer) node.

Also both Panasonic Corporation and Renesas Technology (News - Alert) expect the new technology of the 32-nm node to be available soon for the application to mass products.

For more than a decade, since 1998, both the Panasonic Corporation and Renesas Technology have been involved in co-operative ventures in developmental experiments in the field of elemental process technology.

Their joint efforts in the growth of next generation SoC technology had resulted in the creation of a 130 –nm DRAM (Dynamic Random Access Memory) composite process in the year 2001.

This was soon followed by the development of a 90-nm SoC process in the year 2002. Two years later, in 2004, the two companies completed the 90-nm DRAM composite process which was soon followed by the 65-nm SoC process, a year later in 2005. Their next development in this filed was the 45-nm SoC process which was created in 2007.

The new SoCs at 32-nm process node has been equipped with a new metal/high-k transistor technology gate stack structure and interconnect technology. The device also uses a new low-k material, which has a very limited permittivity.

The companies managed to create a complementary metal insulator semi-conductor (CMIS) application by utilizing a CMOS (complementary Metal Oxide Semi-conductor) at a 32-nm node.

At the atomic level an ultra thin film cap layer is finally applied. The introduction of the cap layer at this stage is expected to enhance the transistor efficiency and the transmission of electrical units. This helps in the success of large scale circuits.

The release of the SoCs at the 32-nm node is expected to cut down on costs and raise the efficiency of performance levels as a result of the miniaturization of its design rules.

The two companies have plans to make use of the new improvements on the SoCs at the 32-nm node production process for mobile technologies and digital electronic appliances for household use.