infoTECH Feature

November 01, 2011

EnSilica Introduces eSi-RISC Development Suite 2.5

EnSilica (News - Alert), Ltd., a company specializing in configurable embedded processors, has unveiled the latest eSi-RISC Development Suite v2.5, which can be utilized in evaluating the EnSilica family of eSi-RISC highly configurable and low-power soft processor cores.

This new version includes capabilities for multicore support and showcases better compiler performance and support for ultra-low-power applications. It also offers JTAG debug and control over all processors in the JTAG chain.

Moreover, the company has also increased the compiler performance with the provision of link time optimization (LTO) support that enhances the code density by between 10 and 15 percent through expanding the scope of inter-procedural optimizations to encompass the whole program.

This was made possible by upgrading the optimizing C/C++ compiler to GNU GCC version 4.6.1. and benchmarking the eSi-3250 32-bit processor core using the embedded processor CoreMark benchmark, which is rapidly replacing the traditional Dhrystone MIPS benchmark, according to the company officials.

In addition, optional load-locked and store-conditional instructions have been added to the instruction set to support multicore systems, along with the support for new peripherals including an AMBA AHB-compatible static memory interface for external Flash and SRAM memory, AMBA AHB DMA Engine, AMBA APB I2C Slave and AMBA APB Smart Card interface supporting ISO-7816 standard.

These have been added to the current eSi-Connect portfolio which already includes SPI, UART USB, I2C Master, Ethernet MAC, RTC and Timer peripherals.

For years, EnSilica's eSi-RISC family has been offering a range of high quality, configurable embedded processors, that claim to provide the flexibility to define a range of hardware functions to optimize the silicon area. On–chip memory requirements are reduced through inter-mixed 16-bit and 32-bit instructions, resulting in good code density without compromising performance.

In related news, ISIS IP (News - Alert), a Chinese fabless semiconductor company focusing on DAB/DAB+/DMB baseband solutions, chose EnSilica’s eSi-RISC family of soft processor cores as the MCU for its second-generation DAB baseband solution last year.

Jyothi Shanbhag is a contributing editor for TMCnet. To read more of Jyothi's articles, please visit her columnist page.

Edited by Carrie Schmelkin

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