Cadence TLM Flow with C-to-Silicon Compiler Helps Sunplus Optimize Productivity

Cadence Design Systems (News - Alert) Inc. announced that Sunplus Technology Co., a multimedia IC design company, has selected the Cadence transaction-level modeling (TLM) flow with Cadence C-to-Silicon Compiler for its multimedia system-on-chip (SoC) design.

In a release Cheng-Yuh Wu, director of DVD IC Design Division I at Sunplus, stated, “In order to accelerate system development time, we decided to adopt the Cadence C-to-Silicon Compiler for our next product because it can generate the best quality of results.”

Specializing in electronic design innovations Cadence has designed its TLM approach and technology to help Sunplus boost design team productivity and control development costs. It also ensures the manufacturing of high-quality chips for its TV, set-top box, and DVD offerings.

The transaction-level modeling with Cadence C-to-Silicon Compiler has been deployed to deliver high-level synthesis using which Sunplus engineers can design and verify their chips at a higher level of abstraction.

Also they will be able to try out more architectural options and rapidly re-target IP to achieve performance, power consumption, and cost requirements, said officials.

“C-to-Silicon Compiler, as part of a TLM flow, helps our engineering teams optimize their designs early in the design cycle, including power characteristics. Perhaps most important, we can use a more abstract language - SystemC - than traditional Verilog/VHDL to do our design. This translates into shorter development time for complex designs, with higher IP reuse for subsequent end products,” added Wu.

The TLM flow forms an important part of the Cadence system realization offerings. It offers a connected path from system development down to silicon realization. Also this TLM-driven flow is scalable and can enhance verification productivity resulting in greater IP re-use. This saves time and costs.

Jack Erickson, director, product marketing, System Realization at Cadence remarked, “TLM design and verification continues to grow in importance and industry use as time-to-market pressures mount in the highly competitive consumer electronics markets.”

The open, connected, and scalable approach to system realization employed in the Cadence TLM flow with the C-to-Silicon Compiler enables faster turnaround time for the development and re-use of complex designs. This helps semiconductor and system companies, including Sunplus, to address the challenges of complex system designs, pointed out Erickson.

Cadence Design Systems, Inc. announced that it will be showcasing its integration-ready, flash IP solutions at the 2011 Flash Memory Summit.

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