infoTECH Feature

December 08, 2010

Fujitsu Semiconductor Now Supports Cadence C-to-Silicon Compiler for ASIC Design Flows

Cadence Design Systems, a dealer in electronic design innovation, stated that the Cadence C-to-Silicon Compiler is now supported in Fujitsu (News - Alert) Semiconductor’s ASIC design flows’ high level synthesis.

According to Cadence, the Cadence C-to-Silicon Compiler automatically generates synthesizable RTL for both datapath and control functionality from timed and untimed C/C++/SystemC algorithm descriptions. Achieving quality of results at or above the 90th percentile of manual RTL design while slashing engineering effort by up to 90 percent, C-to-Silicon Compiler bridges the gap between design complexity and efficiency of RTL code generation.

C-to-Silicon Compiler connects high-level synthesis to production implementation to deliver predictable IP development from TLM to GDSII and also a separate Fujitsu subsidiary has already begun using C-to-Silicon Compiler in production on a large-scale design.

"Our customers want to adopt high-level synthesis based on SystemC in order to increase their design and verification productivity, and enable wider re-use of their IP," said Takashi Hasegawa, general manager of SoC Solutions Division for Fujitsu Semiconductor Limited, in a press release. "We have carefully evaluated Cadence C-to-Silicon Compiler, which delivers the capability to handle ECOs at any time, and its contribution to rapid system development. As a result, we have decided to support its use by our customers, and we are planning to use it internally on a production design."

Some of the key features of the Cadence compiler are: it accepts the widest-range of C/C++/SystemC coding styles and constructs, including templates, classes, user-defined types, and certain types of pointers; Embedded Encounter RTL Compiler delivers consistently accurate timing and area information during the entire high-level synthesis process, resulting in signoff-quality RTL for all types of designs; approximately-timed FHMs generated in SystemC simulate 80-90 percent as fast as the original untimed input model, enabling fast verification and early hardware-software co-development; and more.

Officials with Cadence explained that using the C-to-Silicon Compiler technology, engineers can dramatically accelerate product development for various applications and derivative designs. Fujitsu is expected to benefit significantly from the time-to-market benefits inherent in highly reusable product design and verification at a raised level of abstraction.

Nathesh is a contributing editor for TMCnet. To read more of Nathesh's articles, please visit his columnist page.

Edited by Jaclyn Allard

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