Solido Opens Variation Designer Platform for Third Party Integration

Solido Design Automation, a developer of software for reducing variation risk in nanometer designs at the transistor level, reportedly announced it opened up its SPICE-based Variation Designer platform for integration into third party simulators and design environments.

 

Variation Designer was introduced to the market in January 2009. It is reportedly the first truly scalable and extensible solution specifically developed to address variation challenges at the transistor level.

 

Along with Solido’s process-voltage-temperature or “PVT” corner, statistical and proximity applications packages, Variation Designer can be deployed for transistor level design to account for global, local, environmental and proximity related variation effects, the company said.

 

These solutions help customers achieve better designs with reduced variation risk in less time. Customers have been able to achieve designs with 20 percent to 100 percent better area, power, performance, yield and a reduction in variation design time of more than over 50 percent, company officials said.

 

Variation Designer is used across the transistor level design cycle – from PVT corner simulations to statistical analysis – to determine mismatch effects or yield, they added. It is also useful for post-layout verification and, if required, for silicon debug. The platform also provides a systematic and consistent variation design flow for various transistor level design types such as analog/RF, IO, memory or standard cell digital that can be integrated with various simulator and design environments, providing a consistent interface to designers irrespective of their specific tool environments.

 

“As we have deployed Variation Designer at customer sites we have observed that designers greatly appreciate a consistent interface for their transistor level designs,” Amit Gupta, president and CEO of Solido Design Automation, said in a statement.

 

Gupta further said integration with Variation Designer will enable their partners to provide a consistent interface to help their customers reduce variation design risk and also to benefit as additional applications are launched to solve new and existing variation problems.

 

Variation Designer has been deployed for various flows such as Cadence Virtuoso Analog Design Environment or “ADE” with Specter Circuit Simulator, Virtuoso ADE with Synopsys’ (News - Alert) HSPICE Circuit Simulator, and HSPICE netlist, the company said.