infoTECH Feature

August 30, 2011

Cadence Partners with GLOBALFOUNDRIES

Looking to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers, Cadence Design Systems (News - Alert) has teamed with GLOBALFOUNDRIES.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics.

According to Cadence, its Pattern Search and Matching Analysis are embedded in Cadence Litho Physical Analyzer, Cadence Physical Verification System and the unified Cadence Virtuoso custom/analog and Encounter Digital Implementation System solutions. Correlating 100 percent with the signoff flow and successfully used on advanced node production chips, this offers designers the flexibility to leverage the in-design pattern matching and automatic fixing available in Encounter and Virtuoso, the company stated in a press release.

“The Cadence in-design technology reflects our approach to Silicon Realization by moving traditional DFM steps into digital and custom implementation," said Wilbur Luo, group director, product marketing, Silicon Realization Group at Cadence Design Systems. "This enables engineers to tackle potential manufacturing issues earlier in the chip development process -- before these issues become serious, costly problems at the manufacturing stage.”

With the companies' advanced technology, customers can find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing. Rambus (News - Alert) cited a 60 times speedup of DFM signoff. Many of the world's leading technology companies, including Rambus, have successfully applied the in-design DRC+ flow using the silicon-validated 28-nanometer pattern library from GLOBALFOUNDRIES with the help of the proven Cadence "in-design" DFM technology to support the GLOBALFOUNDRIES DRC+ methodology.

Recently, the company showcased its integration-ready, proven flash IP solutions at the 2011 Flash Memory Summit. Cadence is demonstrated design and verification IP that enable the successful integration of flash memory technology into ASICs and SOCs. Combining technology from both Cadence and the Denali acquisition, the company's comprehensive offering enables the rapid deployment of systems for storage, enterprise and networking applications.

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Raju Shanbhag is a contributing editor for TMCnet. To read more of Raju’s articles, please visit his columnist page.

Edited by Rich Steeves
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