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March 12, 2014

Cadence's ARM-based Verification Solution Speeds Mobile, Network, Server Applications Launch

Cadence Design Systems (News - Alert) has expanded its ARM-based design system verification solution to help launch mobile, networking and server applications faster.  The enhancements are expected to hasten the development of new system designs and software for ARM (News - Alert) Cortex-A processor series based systems.

James McNiven, deputy general manager, systems and software group, ARM said, “In the ultra-competitive mobile, network and server markets, our partners are driven by the need to quickly differentiate and deliver the right product inside very tight development windows.”

“The expanding collaboration between ARM and Cadence, and the availability of better ARM-based system design and verification automation, enables our joint partners to focus on innovation and getting their value added products to market faster,” McNiven added.

ARM and Cadence have joined hands to improve the latter’s system development suite’s ARM-based system verification solution.

The new features include an adaptable interconnect performance characterization test suite in the Cadence interconnect workbench. Also the AMBA designer integration will speed-up performance analysis and verification capabilities of the CoreLink CCI-400 system IP and NIC (News - Alert)-400 design tool based systems. 

In addition, pre-verified support of hardware-accurate OS embedded software is enabled by leveraging the Palladium XP II platform with ARMv8 64-bit Cortex processor family Fast Models, which are available via Cadence now.

The system verification solutions include verification IP that supports AMBA 5 coherent hub interface (CHI) protocol which is implemented in the ARM CoreLink CCN-508 system IP. Also the new verification IP works with all industry simulators including the accelerated verification IP for Palladium XP II platforms.

The Cadence Palladium solution for embedded software development is enabled by ARM-based Fast Models. It is designed to bring down system software validation cycle in addition to providing a smoother post-silicon bring-up, said officials.

Recently Cadence unveiled its new Allegro TimingVision environment, which speeds up timing closure by up to 67 percent. Available within Cadence Allegro PCB Designer, TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements. This is an increasingly important capability as data rates increase and supply voltages decrease in today’s advanced protocols, including DDR3/DDR4, PCI (News - Alert) Express, and SATA.

Edited by Stefania Viscusi

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