Many of the consumer electronic and computing devices we use today are made up of embedded chips that perform critical functions. As these devices get smaller and more powerful, chip makers have to find new materials and manufacturing processes to make this possible. This is especially true for solutions that will be part of the Internet of Things (IoT) and wearable technology. Imagination, creator of processor solutions for graphics, video, display, embedded processing, multi-standard communications and connectivity, has introduced the world's first MCU-class CPU IP cores with hardware virtualization.
What this means is the new MIPS (Microprocessor without Interlocked Pipeline Stages) Warrior M-Class will introduce improved security and reliability in a wide range of entry level smart embedded application. This is very important in M2M applications as the issue regarding the robustness of the security of these devices comes under scrutiny. As more devices get connected to health care products and services as well as other applications in which sensitive and personal data is transmitted, new M2M modules with better security platforms have to be deployed.
When an application requires higher level of security, the new M-Class provides a tamper-resistant feature with available countermeasures when an attempt with unauthorized access is detected. It prevents external debug probes from accessing and interrogating the core internals with a secure debug feature.
The new class of entry-level MIPS Series5 Warrior CPUs deliver the highest CoreMark/MHz scores for MCU-class processors, making them the ideal platform for applications in wireless communications, industrial control, cloud computing, storage and more. While these features by themselves are good enough, Imagination has gone one step further by implementing a technology that was until now only reserved for high-end applications, virtualization.
By incorporating hardware virtualization, Imagination is anticipating the needs of organizations not only today but far into the future. The M-class cores implement the MIPS Release 5 architecture, incorporating hardware virtualization, which is based on the 5-stage pipeline architecture allowing it leverage the high performance, comprehensive digital signal processing (DSP)/SIMD features of the previous generation MIPS microAptiv family of cores, as well as the microMIPS Instruction Set Architecture (ISA), which provides up to 30 percent code size reduction over 32-bit only code.
System development benefits include:
The benefit of virtualization in applications where space is limited is, it can be used to implement multiple guest environments to manage secure transmission of sensor data by one guest, while another can deliver other services.
"The exceptional performance and low power credentials of our latest M-class CPUs have already generated a lot of excitement with our key licensees and partners. And with advanced functionality such as virtualization, full FPUs and advanced DSP capabilities, complemented by mature tools both from ourselves and our ecosystem partners such as Mentor Graphics (News - Alert) and Green Hills Software, we're confident you'll be hearing a lot more about MIPS embedded CPUs in the coolest and most disruptive chips and products," said Tony King-Smith (News - Alert), EVP marketing, Imagination.