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November 26, 2012

Renesas Micro Systems Picks Cadence Encounter RTL Compiler for Complex ASIC Designs

Cadence Designs Systems announced that Renesas Micro Systems will be using the Cadence Encounter RTL Compiler in integrated circuits production with complex ASIC designs to benefit from fast turnaround time and reduction in size and cost.

Enabling electronic design innovation and the development of integrated circuits and electronics, Cadence offers software, hardware, IP and services to design and verify semiconductors, consumer electronics and so on.

Kazuyuki Irie, chief professional, SoC Development Division of Renesas Micro Systems said, “Renesas Micro Systems has been working very closely with Cadence to develop best-in-class netlist analysis flows that provide early insights into potential structural issues and inefficiencies. Encounter RTL Compiler solved a problem we had been grappling with for a long while.”

Renesas Micro Systems strives to achieve high-density layout in short turnaround time for its ASIC designs to cater to the requirements of ASIC design development, such as ultra large-scale, high-speed and complex designs. The new solution will help the company tide over problems relating to additional place-and-route cycles while dealing with hot spots and routability and help start production sooner.

Engineers faced routability issues after running place and route tools which needed longer turnaround times. In case of detection of hot spots, they had to run place and route tools to enable utilization, placement congestion, floor planning and circuit optimization.

However, Cadence Encounter RTL Compiler allows structural analysis of a netlist early in the flow. Now, Renesas Micro Systems engineers are able to identify hurdles even before conducting place and route. This helps them reduce turnaround time and avoid congestion hot spots, which in turn optimizes the production process.

“Like many other technology companies, Renesas Micro Systems is seeking an edge in time-to-market and cost,” said Dr. Chi-Ping Hsu, senior vice president of research and development, Silicon Realization Group, at Cadence. “As a key technology in the Cadence RTL-to-signoff flow, RTL Compiler offers unique capabilities that can get products to market faster while meeting today’s aggressive die size requirements.”

Cadence Design Systems (News - Alert) was assigned a patent recently for developing a method and mechanism for implementing extraction for an integrated circuit design with four other co-inventors. The new method defines a system for stitching one or more islands of an integrated circuit design.


Edited by Rachel Ramsey
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