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October 19, 2012

Cadence 3D-IC Technology Clears Validation for TSMC's CoWoS Reference Flow

Cadence Design Systems (News - Alert), Inc., recently announced that its 3D-IC technology has been validated for TSMC’s CoWoS (chip-on-wafer-on-substrate) Reference Flow with the successful development of a CoWoS test vehicle designed with an SoC with Cadence Wide I/O memory controller and PHY IP.

In a statement, Chi-ping Hsu, senior vice president, research, and development, Silicon Realization Group at Cadence, said, "The Cadence 3D-IC technology enables the next generation of high-performance mobile devices, and offers significant benefits in system performance and power efficiency. Our continued work with TSMC on the CoWoS process ensures that the infrastructure is in place to support this important emerging technology."

Cadence's 3D-IC solution has been developed to include validated technologies ranging from the Cadence Encounter RTL-to-signoff and Virtuoso custom/analog platforms in addition to the Cadence system-in-package products, and the Sigrity power-aware chip/package/board signal integrity solution. 

The CoWoS combo bump cells from TSMC that serve to simplify bump assignment will now feature within the Cadence Encounter Digital Implementation (EDI) System, QRC Extraction, and Cadence Physical Verification System. Providing support for the CoWoS Reference Flow are a CoWoS design kit and silicon validation results from a TSMC test vehicle. The decision by TSMC to go with Cadence's high bandwidth, low power Wide I/O controller and PHY Design IP solution was to ensure easy connectivity with the SoC to Wide I/O DRAM via the use of CoWoS technology which comes with a peak data rate of over 100Gbit/sec for memory interface.

Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, said, "TSMC continues to work closely with Cadence to bring 3D-IC to the industry. We have invested three years with OIP ecosystem partners to prepare the CoWoS design flow for production, and now we're ready to enable customers' 3D-IC designs with TSMC CoWoS technology."

Engineers working on complex designs are provided with a number of benefits by 3D-IC technology which include higher performance, reduced power consumption, and smaller form factor. Developed as an integrated process technology, TSMC's CoWoS combines with multiple chips in a single device to effectively minimize power and form factor while boosting system performance.

Edited by Rich Steeves

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