Cadence Design Systems (News - Alert) Inc., a company specializing in creating integrated circuits and electronics, has introduced a new verification debug product named Incisive Debug Analyzer, specifically used for RTL, testbench and SoC verification.
According to Cadence officials, SoC companies usually spend 50 percent of their overall verification effort in debug, and Incisive Debug Analyzer can be a perfect fit for these companies to cut down the verification bottleneck using unique debug features offered by the new analyzer.
Added features include integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take users directly to the point of interest in either the source code or the waveform database. The debugger also offers users with relevant debug investigation information that allows them to easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.
“Our customers have been seeking a comprehensive RTL, testbench and SoC debug solution to cut through the bottleneck of verification debug," said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence. "Incisive Debug Analyzer provides them with the capabilities, accuracy, flexibility and speed to isolate and fix their bugs in record time."
Incisive Debug Analyzer is backed with innovative debug technology that has helped users to fix bugs in minutes that would have previously taken hours to debug, including detection of the root cause of complex multithreaded behaviors in HDL design.
This new Debug Analyzer works fine with the existing Incisive debug flows as well, fully leveraging SimVision for waveform and transaction-level debug.
Company officials confirmed that the exclusive Incisive Debug Analyzer will hit the market by year’s end.