CSR (News - Alert), a provider of silicon and software solutions, has revealed that it has accelerated its low-power, mixed-signal chip tapeout by using the Cadence Encounter Digital Implementation (EDI) System.
The system includes Encounter Digital Implementation System, Cadence Incisive Enterprise Simulator and Cadence Conformal Low Power. The Cadence digital flow helped CSR to tape out a 40-nanometer low-power Bluetooth and Wi-Fi combo chip efficiently, therefore reducing time to market.
The EDI System was designed with multiple supply voltages, ultimately enabling significant power savings and optimizing area and performance. The EDI System’s timing and signal integrity engineering change order (ECO) flow also accelerated the sign-off correlation resulting in faster timing convergence and signal integrity signoff.
“In another recent multi-radio chip tapeout, the Cadence EDI System and low-power design methodology enabled us to effectively implement and optimize a consistent set of design and multi-supply-voltage power domain constraints across a complex digital-driven mixed-signal hierarchy,” said Steven D. Gray, Ph.D., CTO of CSR.
The EDI solution additionally features the new GigaOpt optimization engine, which produces faster results than traditional methods by incorporating multiple CPUs. The integrated CCOpt technology unifies clock tree synthesis with logic/physical optimization ensuring power, performance and area enhancements, officials said.
Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence, said that “the demand for low-power mixed-signal designs for consumer electronics is skyrocketing,” and that “the CSR design team chose Cadence for our mature and comprehensive low-power solutions that meet the most pressing challenges of complex SoC design.”
“The Encounter digital flow provided a predictable design closure path, meeting and exceeding CSR’s stringent design and time to market requirements. We worked closely with CSR to help them achieve tapeout success for this innovative low-power and mixed-signal SoC,” Hsu added.
Recently, STMicroelectronics a semiconductor provider, leveraged the Cadence signoff solutions to reduce multiple weeks from its design schedule on a 28-nanometer system-on-chip (SoC) besides accelerating time to market in the tapeout of an advanced SoC.