This week at the DesignCon 2011 in Santa Clara, Calif., premier technology licensing company Rambus, Inc. disclosed developments in advanced differential and single-ended signaling technologies. As a result, advanced differential signaling for SoC-to-memory interface has achieved 20 gigabits per second (Gbps) data rate, while the single-ended memory signaling has been extended to an unparalleled speed of 12.8 Gbps. In addition, Rambus (News - Alert) has also developed innovations which enable a seamless transition for memory architectures from single-ended to differential signaling as data rates rise to meet the performance requirements of future-generation graphics and gaming systems
According to Rambus, the latest technology advancements of Terabyte Bandwidth Initiative enable unmatched power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. Rambus said that it has achieved a power efficiency of 6 mW per Gbps when operating at 20 Gbps in a 40-nm process silicon test vehicle. These innovations address critical system challenges to extending signaling rates by addressing power efficiency and compatibility needs, said the developer
“We have paved multiple paths for the industry by providing solutions that extend single-ended signaling beyond today’s limits and developing the means for a seamless transition to differential signaling,” said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus, in a statement. “By advancing data rates in an extremely power-efficient way and enabling compatibility to current industry-standard memories, we have removed the technical and business barriers for customers to achieve unprecedented capabilities in their products,” she noted.
Graphics cards and game consoles are the marquee performance products for consumers. The demand for photorealistic game play, 3D images, and a richer end-user experience is constantly pushing system and memory requirements higher. Today’s high-end graphics processors support as much as 128 gigabytes per second (GBps) of memory bandwidth, and future generations will push memory bandwidth to upwards of one terabyte per second (TBps).
Through the Terabyte Bandwidth Initiative, Rambus has developed key innovations using its renowned signaling and memory architecture expertise. These Rambus patented innovations include Fully Differential Memory Architecture (FDMA), FlexLink C/A and 32X data rate. The latest addition to these innovations, FlexMode interface technology, enables support of both differential and single-ended memory interfaces in a single SoC package design. FlexMode technology achieves this with no additional pins through programmable assignment of signaling I/Os to either data or command/address.