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TMCNet:  Thursday is Training Day - Tradition Continues at the 54th Design Automation Conference

[May 16, 2017]

Thursday is Training Day - Tradition Continues at the 54th Design Automation Conference

DAC, the premier conference devoted to the design and automation of electronic systems, is excited to once again host Thursday is Training Day allowing DAC attendees to attend high quality sessions in popular subjects. The 54th DAC will be held at the Austin Convention Center in Austin, Texas from June 18 - 22, 2017. Conference registration is now open, including sign-up for "Thursday is Training Day," as well as the new free "Lunch 'N' Learn" taster session on Machine Learning on Wednesday.

All sessions are taught by highly respected instructors who are each subject matter experts in their own right and who each have a wide experience of teaching engineers at all skill levels. On Wednesday, the special one hour taster session (including lunch) is provided by Doulos on the subject of Python for Machine Learning. On Thursday attendees may choose sessions from three parallel tracks with the option to select both the morning and afternoon sessions from the same track, or mix-and-match sessions from two different tracks or attend a single half-day session. Training sessions on SystemVerilog, UVM, and Python are taught by Doulos and C++ by Trull Consulting.

Lunch 'N' Learn Wednesday, June 21:

  • Python for Scientific Computing and Machine Learning
    • Lunch sponsored by Synopsys (News - Alert)
    • Registration for the Lunch 'N' Learn: a rel="nofollow" href="http://cts.businesswire.com/ct/CT?id=smartlink&url=http%3A%2F%2Fbit.ly%2F2oKiPt6&esheet=51560633&newsitemid=20170516006642&lan=en-US&anchor=http%3A%2F%2Fbit.ly%2F2oKiPt6&index=2&md5=a682be5b7a3628952f21919147596b1d" rel="nofollow">http://bit.ly/2oKiPt6

Thursday is Training Day Tracks:

  • Track 1: SystemVerilog & UVM Coding
    • Part 1: How to Build Class-Based Verification Environments in SystemVerilog
    • Part 2: Learn UVM using the Easier UVM Coding Guidelines and Code Generator
  • Track 2: SystemVerilog Verification and Python Language
    • Part 1: Formal Verification using SystemVerilog Assertions
    • Part 2: The Python Language: Become a Pythoneer!
  • Track 3: Raising your C++ Game (two parts)

Session details, including summaries, presenter information and room numbers, can be found at: https://dac.com/events/training. Reserve a seat when you register for DAC at www.dac.com.

About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic System Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineers (IEEE (News - Alert)), and is supported by ACM's Special Interest Group on Design.

Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.


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