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TMCNet:  Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

[August 05, 2014]

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

(Marketwire Via Acquire Media NewsEdge) ALAMEDA, CA -- (Marketwired) -- 08/05/14 -- Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers as the front end to the Wasga� Compiler Design Suite for field programmable gate array (FPGA)-based prototyping.

"Verific was an easy choice for us," remarks Hayder Mrabet, chief executive officer of Flexras Technologies. "Its reputation for high-quality software and superior support and service is unmatched. We've been completely satisfied with both." The Wasga Compiler is a timing-driven partitioning tool for system-on-chip (SoC) rapid prototyping. It automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity and clock frequency constraints required for running software applications in near real time.

"As Flexras is proving, FPGA-based prototyping provides the speed and accuracy necessary to develop and validate complex software integration prior to silicon," adds Rob Dekker, Verific's chief technology officer. "Verific is pleased to offer front-end software that will be implemented in this type of verification solution." The electronic design automation (EDA) and FPGA industry uses Verific's software to serve as the front end for tools used for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About FlexrasFlexras Technologies develops and commercializes EDA partitioning tools for the FPGA and SoC markets. Flexras proprietary and proven timing-driven partitioning technology are used by world leading semiconductor manufacturers, and licensed to FPGA-based systems providers. Flexras addresses growing SoCs development complexity and risks by accelerating cost effective rapid prototyping with multi-FPGA-based systems. Flexras Technologies is headquartered in Paris-Saint Denis France. For more information, please visit www.flexras.com.

About Verific Design AutomationVerific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: info@verific.com. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact: Nanette Collins Public Relations for Verific (617) 437-1822 Email Contact Source: Verific

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