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TMCNet:  Avery Design Systems Revs PCIe and eMMC VIP and Introduces VIPs for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD

[May 28, 2014]

Avery Design Systems Revs PCIe and eMMC VIP and Introduces VIPs for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD

ANDOVER, Mass. --(Business Wire)--

Avery Design Systems Inc., a leader in verification IP, today announced availability of a major new release of the flagship PCIe VIP, major VIP update for eMMC 5.X, and new VIP introductions for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD. The Avery VIP portfolio is now 100% implemented in native SystemVerilog UVM.

Avery supports over 25 standard protocols ranging from high speed IO, SSD/HDD, mobile, embedded storage, memory, and control bus protocols. Avery VIPs offer the most complete verification solutions consisting of SystemVerilog UVM compliant models and environment, protocol checkers, directed and random compliance test suites, and reference verification frameworks. Advanced debug features include multi-level analyzer trackers to visualize data and control flow through the protocol stacks. Compliance verification services are offered for all VIPs.

"Avery offers semiconductor companies and IP vendors an extensiv VIP portfolio including highly differentiated solutions for PCIe, the most complete SDD/HDD protocol support for host and device models, host controller verification solutions for USB xHCI, UFS HCI, SD and eMMC HC, and DDR4 PHY and RDIMM verification", said Chilai Huang, president of Avery Design Systems. "With the release of new VIPs for HMC and LRDIMM (memory), Soundwire (MIPI connectivity), SD/UHS-II (memory cards), and CAN FD (automotive network), Avery expands the quality and breadth of our VIP solutions in important areas such as mobile, automotive, and high performance computing."

Visit us at the Design Automation Conference (DAC) June 2-4 in booth #1225 to learn more about Avery VIP solutions.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, low power retention register synthesis, and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI (News - Alert) Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics (News - Alert) Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.


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