|[March 04, 2014]
Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard
WILSONVILLE, Ore. --(Business Wire)--
Graphics Corp. (NASDAQ:MENT), today announced it has proposed that a
standards committee be formed to investigate the standardization of a
graph-based test specification standard. To underscore this endeavor,
Mentor will make a technical donation of its existing graph-based test
specification format to jump-start the standardization effort.
"The Mentor graph-based specification technology brings compelling new
value to the verification domain with its capabilities for quickly and
exhaustively covering the device state space," said Peter Jensen, owner
and managing director, SyoSil. "This lets us use a unified graph-based
description for traditional coverage-driven verification using UVM at
the block level, as well as intelligent software-driven verification
using embedded C test programs at the system level."
"Having access to the most advanced functional verification
methodologies is essential to maximize electronic design and
verification efficiency, and we have seen customers realize a ten-fold
gain in productivity through the adoption of graph-based test
technology," said John Lenyo, vice president and general manager, Design
Verification Technology Division, Mentor Graphics (News - Alert). "Based on customer
feedback, we're moving forward to recommend and facilitte a standards
effort that brings significant benefits to a large number of users, and
opens the door to technology innovation."
Benefits of a Graph-Based Test Specification
The benefits of graph-based test specification are threefold. First, it
reduces the time spent writing and debugging tests by 50% or more.
Verification engineers can use the graph-based specification format to
describe the exact same test universes currently described in their
existing SystemVerilog UVM constraint-based tests, in less than half the
lines of code, without any change to the test intent. This also means a
reduction in the number of test bugs, enabling verification engineers to
focus on debugging their designs, not their tests.
Second, the graph-based test specification format naturally supports
multiple design languages and multiple verification environments
enabling re-use across both design context and verification engines. The
same graph-based test specification can be used in a SystemVerilog UVM
testbench environment for block-level simulation, as well as in an
embedded C test program for system-level emulation. It can also be used
to generate instructions for microprocessor instruction set
verification, and it can even be used on target hardware including FPGA
prototyping and post-silicon validation.
Third, the abstract nature of a graph-based test specification lets tool
implementations execute the test specification in different ways
according to verification requirements. For example, a tool with a
graph-based test specification can be instructed to execute the test
specification in a systematic way to quickly achieve functional coverage
during the early stages of a verification project. At a later time, the
tool can be instructed to execute the test specification in a completely
random manner to produce soak tests on a simulation farm for regression
Mentor's Donation to the Graph-Based Test Specification Standards
The graph-based specification format is not new to verification. It is
based on the standard Backus-Naur Form (BNF), pioneered by IBM (News - Alert), and has
been used by many companies to automate compiler testing. Its natural
atomic architecture closely mimics the structure of a typical design
specification, making requirements mapping easy and straightforward. The
graph-based specification format being donated by Mentor Graphics has
been augmented to support VLSI design verification across all standard
environments and languages including Verilog, VHDL, SystemVerilog, e,
SystemC, C/C++, assembly code.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and
software design solutions, providing products, consulting services and
award-winning support for the world's most successful electronic,
semiconductor and systems companies. Established in 1981, the company
reported revenues in the last fiscal year in excess of $1.15 billion.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics is a registered trademark of Mentor Graphics
Corporation. All other company or product names are the registered
trademarks or trademarks of their respective owners.
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