|[December 20, 2012]
Samsung Delivers Strong 14nm FinFET Logic Process and Design Infrastructure for Advanced Mobile SoC Customers
SEOUL, South Korea --(Business Wire)--
Samsung (News - Alert) Electronics Co., Ltd., a global leader in advanced semiconductor
solutions, today announced that it reached another milestone in the
development of 14-nanometer (nm) FinFET process technology with the
successful tape-out of multiple development vehicles in collaboration
with its key design and IP partners. In addition, Samsung has signed an
agreement with ARM (News - Alert)® for 14nm physical IP and libraries. This agreement
is the latest in a series from Samsung and ARM that has delivered
production proven SoC enablement. Samsung, together with its ecosystem
partners, is in a position to offer leading edge customers a robust
design infrastructure to drive an ever expanding advanced mobile SoC
"As we move closer to true mobile computing, chip designers are eager to
take advantage of the gains in performance and significantly lower power
of 14nm FinFET to deliver PC like user experience on a mobile device,"
said Dr. Kyu-Myung Choi, senior vice president of System LSI
infrastructure design center, Device Solutions Division, Samsung
Electronics. "The design complexities at 14nm require complete harmony
between the process technology, design methodology, tools and IPs. We
are synchronizing all the key elements so our customers can deliver
their newest chips to market quickly and efficiently."
As part of its 14nm FinFET development process, Samsung, and its
ecosystem partners - ARM, Cadence, Mentor and Synopsys (News - Alert) - taped out
multiple test chips ranging from a full ARM® Cortex™-A7 processor
implementation to a SRAM-based chip capable of operation near threshold
voltage levels as well as an array of analog IP.
The full ARM Cortex-A7 processor test chip tape-out represents a
significant milestone for silicon manufacturing for the fabless
ecosystem. The Cortex-A7 implementation on FinFET demonstrates the
low-power component of the ARM big.LITTLE™ processor
configuration/technology strategy for mobile computing platforms. The
Samsung 14nm FinFET enablement for SoC design provides improved leakage
and dynamic power advantages to the expanding mobile computing market.
This collaboration builds on the long-standing partnership between
Samsung and ARM including SoC design enablement for the production
proven 32/28nm High-K Metal Gate (HKMG) technology. Enabling SoC design
on FinFET allows the continued fast pace of innovation that is the
hallmark of the mobile market segment.
The Cortex-A7 processor test chip was implemented by Cadence in
collaboration with ARM and Samsung. Cadence delivered a full
RTL-to-signoff flow, building upon a tool set that has been thoroughly
tested on 20nm designs requiring automted double patterning. The tight
collaboration with Samsung and ARM enabled Cadence to hone its
technology for 14nm FinFET designs, paving the way for 14nm market
readiness. ARM used Cadence tools to develop the 14nm FinFET libraries,
and Cadence tools were also used for a full-flow RTL-to-signoff tapeout
of the processor core on Samsung's 14nm FinFET process, as well as
chip-level integration and verification.
Samsung used Synopsys tools optimized for FinFET devices to implement
additional IP on this vehicle, including low power SRAMs intended to
operate with the power supply close to threshold voltage levels. The
move from two-dimensional transistors to three-dimensional transistors
introduces several new IP and EDA tool challenges including modeling.
The multi-year collaboration between Samsung and Synopsys has delivered
foundational modeling technologies for 3D parasitic extraction, circuit
simulation and physical design-rule support of FinFET devices.
Samsung is also extending their work with Mentor to enable a complete
solution at 14nm FinFET that addresses customer challenges in design,
validation, manufacturing co-optimization, and post-design production
ramps.�The collaborative efforts leverage the unique capabilities of
Samsung's processes, while helping designers deal with the complexities
of multi-patterning lithography, FinFET transistors, and more complex
Silicon-based PDK Availability
With its process design kit available to customers today, customers can
start designing with models, design rule manuals and technology files
that have been developed based on silicon results from previous 14nm
FinFET test chips run in Samsung's R&D facilities. This PDK includes
design flows, routers and other design enablement features to support
new device structures, local interconnects, and advanced routing rules.
The investments that Samsung is making into the entire ecosystem at 14nm
will give customers early access to all elements of the design
infrastructure to accelerate their chip development.
About Samsung Electronics Co., Ltd.
Samsung Electronics Co., Ltd. is a global leader in semiconductor,
telecommunication, digital media and digital convergence technologies
with 2011 consolidated sales of US$143.1 billion. Employing
approximately 227,000 people in 203 offices across 75 countries, the
company operates two separate organizations to coordinate its nine
independent business units: Digital Media & Communications, comprising
Visual Display, Mobile Communications, Telecommunication Systems,
Digital Appliances, IT Solutions, and Digital Imaging; and Device
Solutions, consisting of Memory, System LSI and LED. For more
information, please visit www.samsung.com.
Samsung and the stylized Samsung design are trademarks and service
marks of Samsung Electronics Co., Ltd. Other trademarks are the property
of their respective owners.
"Implementing the Cortex-A7 processor-based test chip on the 14nm FinFET
process combines the most energy-efficient ARM applications processor
with Samsung's advanced low-power manufacturing process to demonstrate
our ongoing commitment to low-power leadership. Our early collaboration
with Samsung during its process technology development helps optimize
ARM Artisan® physical IP and maximize the benefits available from
advanced silicon manufacturing."
Dr. Dipesh Patel
President and General Manager, Physical IP Division
"Our leading-edge customers see the performance and low-power advantages
of 14nm FinFET design, and they've asked us to help them get there ASAP.
The Cadence end-to-end design flow including signoff enables engineers
working along the cutting edge to bring the benefits of 14nm FinFET
design to the mobile and server markets."
Dr. Chi-Ping Hsu
Vice President, Research and Development, Silicon Realization Group
Mentor Graphics (News - Alert)
"Mentor and Samsung continue to be committed to providing the most
advanced solutions for our mutual customers in both semiconductor
process technology, and the associated ecosystem required to leverage
new offerings like FinFET transistors. Mentor has always driven its
technology development in partnership with key customers. Our
collaboration with Samsung is yielding results that designers can access
Vice President and
General Manager, Design to Silicon Division
"Our successful 14nm FinFET tapeouts with Samsung�represent a major
milestone in the multi-year collaboration between Samsung and Synopsys
to deliver optimized FinFET-ready EDA tool and IP enablement for the
Sr Vice President,
Marketing & Strategic Development
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